upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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128 lines
2.9 KiB
128 lines
2.9 KiB
/*
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* (C) Copyright 2007-2009 DENX Software Engineering
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*
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*/
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#include <common.h>
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#include <command.h>
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#include <asm/io.h>
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#include <asm/processor.h>
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DECLARE_GLOBAL_DATA_PTR;
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#if defined(CONFIG_IDE_RESET)
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void ide_set_reset (int idereset)
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{
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volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
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debug ("ide_set_reset(%d)\n", idereset);
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if (idereset) {
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out_be32(&im->pata.pata_ata_control, 0);
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} else {
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out_be32(&im->pata.pata_ata_control, FSL_ATA_CTRL_ATA_RST_B);
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}
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udelay(100);
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}
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void init_ide_reset (void)
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{
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debug ("init_ide_reset\n");
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/*
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* Clear the reset bit to reset the interface
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* cf. RefMan MPC5121EE: 28.4.1 Resetting the ATA Bus
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*/
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ide_set_reset(1);
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/* Assert the reset bit to enable the interface */
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ide_set_reset(0);
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}
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#define CALC_TIMING(t) (t + period - 1) / period
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int ide_preinit (void)
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{
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volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
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long t;
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const struct {
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short t0;
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short t1;
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short t2_8;
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short t2_16;
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short t2i;
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short t4;
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short t9;
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short tA;
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} pio_specs = {
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.t0 = 600,
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.t1 = 70,
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.t2_8 = 290,
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.t2_16 = 165,
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.t2i = 0,
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.t4 = 30,
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.t9 = 20,
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.tA = 50,
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};
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union {
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u32 config;
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struct {
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u8 field1;
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u8 field2;
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u8 field3;
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u8 field4;
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}bytes;
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} cfg;
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debug ("IDE preinit using PATA peripheral at IMMR-ADDR %08x\n",
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(u32)&im->pata);
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/* Set the reset bit to 1 to enable the interface */
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ide_set_reset(0);
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/* Init timings : we use PIO mode 0 timings */
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t = 1000000000 / gd->ips_clk; /* period in ns */
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cfg.bytes.field1 = 3;
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cfg.bytes.field2 = 3;
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cfg.bytes.field3 = (pio_specs.t1 + t) / t;
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cfg.bytes.field4 = (pio_specs.t2_8 + t) / t;
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out_be32(&im->pata.pata_time1, cfg.config);
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cfg.bytes.field1 = (pio_specs.t2_8 + t) / t;
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cfg.bytes.field2 = (pio_specs.tA + t) / t + 2;
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cfg.bytes.field3 = 1;
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cfg.bytes.field4 = (pio_specs.t4 + t) / t;
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out_be32(&im->pata.pata_time2, cfg.config);
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cfg.config = in_be32(&im->pata.pata_time3);
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cfg.bytes.field1 = (pio_specs.t9 + t) / t;
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out_be32(&im->pata.pata_time3, cfg.config);
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debug ("PATA preinit complete.\n");
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return 0;
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}
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#endif /* defined(CONFIG_IDE_RESET) */
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