upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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103 lines
2.6 KiB
103 lines
2.6 KiB
/*
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* (C) Copyright 2002
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* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
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* Alex Zuepke <azu@sysgo.de>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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/* ------------------------------------------------------------------------- */
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/*
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* Miscelaneous platform dependent initialisations
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*/
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int board_init (void)
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{
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DECLARE_GLOBAL_DATA_PTR;
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/* memory and cpu-speed are setup before relocation */
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/* but if we use InfernoLoader, we must do some inits here */
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#ifdef CONFIG_INFERNO
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{
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unsigned long temp;
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__asm__ __volatile__(/* disable MMU, enable icache */
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"mrc p15, 0, %0, c1, c0\n"
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"bic %0, %0, #0x00002000\n"
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"bic %0, %0, #0x0000000f\n"
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"orr %0, %0, #0x00001000\n"
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"orr %0, %0, #0x00000002\n"
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"mcr p15, 0, %0, c1, c0\n"
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/* flush caches */
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"mov %0, #0\n"
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"mcr p15, 0, %0, c7, c7, 0\n"
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"mcr p15, 0, %0, c8, c7, 0\n"
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: "=r" (temp)
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:
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: "memory");
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/* setup PCMCIA timing */
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temp = 0xa0000018;
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*(unsigned long *)temp = 0x00060006;
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}
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#endif /* CONFIG_INIT_CRITICAL */
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/* arch number for shannon */
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gd->bd->bi_arch_number = 97;
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/* adress of boot parameters */
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gd->bd->bi_boot_params = 0xc0000100;
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return 0;
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}
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int dram_init (void)
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{
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#if defined(PHYS_SDRAM_1) || defined(PHYS_SDRAM_2) || \
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defined(PHYS_SDRAM_3) || defined(PHYS_SDRAM_4)
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DECLARE_GLOBAL_DATA_PTR;
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bd_t *bd = gd->bd;
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#endif
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#ifdef PHYS_SDRAM_1
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bd->bi_dram[0].start = PHYS_SDRAM_1;
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bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
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#endif
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#ifdef PHYS_SDRAM_2
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bd->bi_dram[1].start = PHYS_SDRAM_2;
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bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
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#endif
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#ifdef PHYS_SDRAM_3
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bd->bi_dram[2].start = PHYS_SDRAM_3;
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bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE;
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#endif
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#ifdef PHYS_SDRAM_4
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bd->bi_dram[3].start = PHYS_SDRAM_4;
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bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE;
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#endif
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return (0);
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}
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