upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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220 lines
6.6 KiB
220 lines
6.6 KiB
/*
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* (C) Copyright 2008
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* Benjamin Warren, biggerbadderben@gmail.com
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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/*
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* netdev.h - definitions an prototypes for network devices
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*/
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#ifndef _NETDEV_H_
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#define _NETDEV_H_
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/*
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* Board and CPU-specific initialization functions
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* board_eth_init() has highest priority. cpu_eth_init() only
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* gets called if board_eth_init() isn't instantiated or fails.
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* Return values:
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* 0: success
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* -1: failure
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*/
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int board_eth_init(bd_t *bis);
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int cpu_eth_init(bd_t *bis);
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/* Driver initialization prototypes */
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int altera_tse_initialize(u8 dev_num, int mac_base,
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int sgdma_rx_base, int sgdma_tx_base,
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u32 sgdma_desc_base, u32 sgdma_desc_size);
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int at91emac_register(bd_t *bis, unsigned long iobase);
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int au1x00_enet_initialize(bd_t*);
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int ax88180_initialize(bd_t *bis);
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int bcm_sf2_eth_register(bd_t *bis, u8 dev_num);
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int bfin_EMAC_initialize(bd_t *bis);
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int calxedaxgmac_initialize(u32 id, ulong base_addr);
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int cs8900_initialize(u8 dev_num, int base_addr);
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int davinci_emac_initialize(void);
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int dc21x4x_initialize(bd_t *bis);
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int designware_initialize(ulong base_addr, u32 interface);
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int dm9000_initialize(bd_t *bis);
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int dnet_eth_initialize(int id, void *regs, unsigned int phy_addr);
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int e1000_initialize(bd_t *bis);
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int eepro100_initialize(bd_t *bis);
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int enc28j60_initialize(unsigned int bus, unsigned int cs,
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unsigned int max_hz, unsigned int mode);
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int ep93xx_eth_initialize(u8 dev_num, int base_addr);
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int eth_3com_initialize (bd_t * bis);
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int ethoc_initialize(u8 dev_num, int base_addr);
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int fec_initialize (bd_t *bis);
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int fecmxc_initialize(bd_t *bis);
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int fecmxc_initialize_multi(bd_t *bis, int dev_id, int phy_id, uint32_t addr);
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int ftgmac100_initialize(bd_t *bits);
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int ftmac100_initialize(bd_t *bits);
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int ftmac110_initialize(bd_t *bits);
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int greth_initialize(bd_t *bis);
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void gt6426x_eth_initialize(bd_t *bis);
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int ks8695_eth_initialize(void);
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int ks8851_mll_initialize(u8 dev_num, int base_addr);
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int lan91c96_initialize(u8 dev_num, int base_addr);
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int macb_eth_initialize(int id, void *regs, unsigned int phy_addr);
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int mcdmafec_initialize(bd_t *bis);
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int mcffec_initialize(bd_t *bis);
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int mpc512x_fec_initialize(bd_t *bis);
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int mpc5xxx_fec_initialize(bd_t *bis);
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int mpc82xx_scc_enet_initialize(bd_t *bis);
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int mvgbe_initialize(bd_t *bis);
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int mvneta_initialize(bd_t *bis, int base_addr, int devnum, int phy_addr);
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int natsemi_initialize(bd_t *bis);
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int ne2k_register(void);
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int npe_initialize(bd_t *bis);
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int ns8382x_initialize(bd_t *bis);
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int pcnet_initialize(bd_t *bis);
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int ppc_4xx_eth_initialize (bd_t *bis);
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int rtl8139_initialize(bd_t *bis);
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int rtl8169_initialize(bd_t *bis);
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int scc_initialize(bd_t *bis);
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int sh_eth_initialize(bd_t *bis);
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int skge_initialize(bd_t *bis);
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int smc91111_initialize(u8 dev_num, int base_addr);
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int smc911x_initialize(u8 dev_num, int base_addr);
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int sunxi_emac_initialize(bd_t *bis);
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int sunxi_gmac_initialize(bd_t *bis);
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int tsi108_eth_initialize(bd_t *bis);
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int uec_standard_init(bd_t *bis);
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int uli526x_initialize(bd_t *bis);
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int armada100_fec_register(unsigned long base_addr);
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int xilinx_axiemac_initialize(bd_t *bis, unsigned long base_addr,
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unsigned long dma_addr);
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int xilinx_emaclite_of_init(const void *blob);
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int xilinx_emaclite_initialize(bd_t *bis, unsigned long base_addr,
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int txpp, int rxpp);
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int xilinx_ll_temac_eth_init(bd_t *bis, unsigned long base_addr, int flags,
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unsigned long ctrl_addr);
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int zynq_gem_of_init(const void *blob);
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int zynq_gem_initialize(bd_t *bis, phys_addr_t base_addr,
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int phy_addr, u32 emio);
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/*
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* As long as the Xilinx xps_ll_temac ethernet driver has not its own interface
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* exported by a public hader file, we need a global definition at this point.
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*/
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#if defined(CONFIG_XILINX_LL_TEMAC)
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#define XILINX_LL_TEMAC_M_FIFO 0 /* use FIFO Ctrl */
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#define XILINX_LL_TEMAC_M_SDMA_PLB (1 << 0)/* use SDMA Ctrl via PLB */
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#define XILINX_LL_TEMAC_M_SDMA_DCR (1 << 1)/* use SDMA Ctrl via DCR */
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#endif
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/* Boards with PCI network controllers can call this from their board_eth_init()
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* function to initialize whatever's on board.
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* Return value is total # of devices found */
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static inline int pci_eth_init(bd_t *bis)
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{
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int num = 0;
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#ifdef CONFIG_PCI
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#ifdef CONFIG_EEPRO100
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num += eepro100_initialize(bis);
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#endif
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#ifdef CONFIG_TULIP
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num += dc21x4x_initialize(bis);
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#endif
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#ifdef CONFIG_E1000
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num += e1000_initialize(bis);
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#endif
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#ifdef CONFIG_PCNET
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num += pcnet_initialize(bis);
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#endif
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#ifdef CONFIG_NATSEMI
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num += natsemi_initialize(bis);
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#endif
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#ifdef CONFIG_NS8382X
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num += ns8382x_initialize(bis);
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#endif
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#if defined(CONFIG_RTL8139)
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num += rtl8139_initialize(bis);
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#endif
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#if defined(CONFIG_RTL8169)
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num += rtl8169_initialize(bis);
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#endif
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#if defined(CONFIG_ULI526X)
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num += uli526x_initialize(bis);
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#endif
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#endif /* CONFIG_PCI */
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return num;
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}
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/*
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* Boards with mv88e61xx switch can use this by defining
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* CONFIG_MV88E61XX_SWITCH in respective board configheader file
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* the stuct and enums here are used to specify switch configuration params
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*/
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#if defined(CONFIG_MV88E61XX_SWITCH)
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/* constants for any 88E61xx switch */
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#define MV88E61XX_MAX_PORTS_NUM 6
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enum mv88e61xx_cfg_mdip {
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MV88E61XX_MDIP_NOCHANGE,
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MV88E61XX_MDIP_REVERSE
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};
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enum mv88e61xx_cfg_ledinit {
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MV88E61XX_LED_INIT_DIS,
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MV88E61XX_LED_INIT_EN
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};
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enum mv88e61xx_cfg_rgmiid {
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MV88E61XX_RGMII_DELAY_DIS,
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MV88E61XX_RGMII_DELAY_EN
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};
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enum mv88e61xx_cfg_prtstt {
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MV88E61XX_PORTSTT_DISABLED,
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MV88E61XX_PORTSTT_BLOCKING,
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MV88E61XX_PORTSTT_LEARNING,
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MV88E61XX_PORTSTT_FORWARDING
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};
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struct mv88e61xx_config {
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char *name;
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u8 vlancfg[MV88E61XX_MAX_PORTS_NUM];
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enum mv88e61xx_cfg_rgmiid rgmii_delay;
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enum mv88e61xx_cfg_prtstt portstate;
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enum mv88e61xx_cfg_ledinit led_init;
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enum mv88e61xx_cfg_mdip mdip;
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u32 ports_enabled;
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u8 cpuport;
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};
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/*
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* Common mappings for Internal VLANs
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* These mappings consider that all ports are useable; the driver
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* will mask inexistent/unused ports.
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*/
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/* Switch mode : routes any port to any port */
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#define MV88E61XX_VLANCFG_SWITCH { 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F }
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/* Router mode: routes only CPU port 5 to/from non-CPU ports 0-4 */
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#define MV88E61XX_VLANCFG_ROUTER { 0x20, 0x20, 0x20, 0x20, 0x20, 0x1F }
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int mv88e61xx_switch_initialize(struct mv88e61xx_config *swconfig);
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#endif /* CONFIG_MV88E61XX_SWITCH */
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struct mii_dev *fec_get_miibus(uint32_t base_addr, int dev_id);
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#ifdef CONFIG_PHYLIB
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struct phy_device;
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int fec_probe(bd_t *bd, int dev_id, uint32_t base_addr,
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struct mii_dev *bus, struct phy_device *phydev);
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#else
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/*
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* Allow FEC to fine-tune MII configuration on boards which require this.
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*/
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int fecmxc_register_mii_postcall(struct eth_device *dev, int (*cb)(int));
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#endif
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#endif /* _NETDEV_H_ */
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