upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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89 lines
1.8 KiB
89 lines
1.8 KiB
/*
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* Copyright (C) 2011 Vladimir Zapolskiy <vz@mleia.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/clk.h>
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#include <asm/arch/uart.h>
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#include <asm/io.h>
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#include <serial.h>
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#include <linux/compiler.h>
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DECLARE_GLOBAL_DATA_PTR;
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static struct hsuart_regs *hsuart = (struct hsuart_regs *)HS_UART_BASE;
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static void lpc32xx_serial_setbrg(void)
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{
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u32 div;
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/* UART rate = PERIPH_CLK / ((HSU_RATE + 1) x 14) */
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div = (get_serial_clock() / 14 + gd->baudrate / 2) / gd->baudrate - 1;
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if (div > 255)
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div = 255;
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writel(div, &hsuart->rate);
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}
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static int lpc32xx_serial_getc(void)
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{
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while (!(readl(&hsuart->level) & HSUART_LEVEL_RX))
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/* NOP */;
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return readl(&hsuart->rx) & HSUART_RX_DATA;
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}
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static void lpc32xx_serial_putc(const char c)
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{
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if (c == '\n')
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serial_putc('\r');
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writel(c, &hsuart->tx);
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/* Wait for character to be sent */
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while (readl(&hsuart->level) & HSUART_LEVEL_TX)
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/* NOP */;
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}
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static int lpc32xx_serial_tstc(void)
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{
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if (readl(&hsuart->level) & HSUART_LEVEL_RX)
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return 1;
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return 0;
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}
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static int lpc32xx_serial_init(void)
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{
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lpc32xx_serial_setbrg();
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/* Disable hardware RTS and CTS flow control, set up RX and TX FIFO */
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writel(HSUART_CTRL_TMO_16 | HSUART_CTRL_HSU_OFFSET(20) |
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HSUART_CTRL_HSU_RX_TRIG_32 | HSUART_CTRL_HSU_TX_TRIG_0,
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&hsuart->ctrl);
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return 0;
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}
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static struct serial_device lpc32xx_serial_drv = {
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.name = "lpc32xx_serial",
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.start = lpc32xx_serial_init,
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.stop = NULL,
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.setbrg = lpc32xx_serial_setbrg,
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.putc = lpc32xx_serial_putc,
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.puts = default_serial_puts,
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.getc = lpc32xx_serial_getc,
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.tstc = lpc32xx_serial_tstc,
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};
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void lpc32xx_serial_initialize(void)
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{
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serial_register(&lpc32xx_serial_drv);
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}
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__weak struct serial_device *default_serial_console(void)
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{
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return &lpc32xx_serial_drv;
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}
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