upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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222 lines
4.8 KiB
222 lines
4.8 KiB
/*
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* (C) Copyright 2009
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* Marvell Semiconductor <www.marvell.com>
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* Written-by: Prafulla Wadaskar <prafulla@marvell.com>
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*
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* Derived from drivers/spi/mpc8xxx_spi.c
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <malloc.h>
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#include <spi.h>
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#include <asm/io.h>
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#include <asm/arch/soc.h>
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#ifdef CONFIG_KIRKWOOD
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#include <asm/arch/mpp.h>
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#endif
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#include <asm/arch-mvebu/spi.h>
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static struct kwspi_registers *spireg =
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(struct kwspi_registers *)MVEBU_SPI_BASE;
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#ifdef CONFIG_KIRKWOOD
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static u32 cs_spi_mpp_back[2];
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#endif
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struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
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unsigned int max_hz, unsigned int mode)
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{
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struct spi_slave *slave;
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u32 data;
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#ifdef CONFIG_KIRKWOOD
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static const u32 kwspi_mpp_config[2][2] = {
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{ MPP0_SPI_SCn, 0 }, /* if cs == 0 */
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{ MPP7_SPI_SCn, 0 } /* if cs != 0 */
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};
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#endif
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if (!spi_cs_is_valid(bus, cs))
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return NULL;
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slave = spi_alloc_slave_base(bus, cs);
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if (!slave)
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return NULL;
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writel(KWSPI_SMEMRDY, &spireg->ctrl);
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/* calculate spi clock prescaller using max_hz */
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data = ((CONFIG_SYS_TCLK / 2) / max_hz) + 0x10;
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data = data < KWSPI_CLKPRESCL_MIN ? KWSPI_CLKPRESCL_MIN : data;
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data = data > KWSPI_CLKPRESCL_MASK ? KWSPI_CLKPRESCL_MASK : data;
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/* program spi clock prescaller using max_hz */
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writel(KWSPI_ADRLEN_3BYTE | data, &spireg->cfg);
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debug("data = 0x%08x\n", data);
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writel(KWSPI_SMEMRDIRQ, &spireg->irq_cause);
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writel(KWSPI_IRQMASK, &spireg->irq_mask);
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#ifdef CONFIG_KIRKWOOD
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/* program mpp registers to select SPI_CSn */
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kirkwood_mpp_conf(kwspi_mpp_config[cs ? 1 : 0], cs_spi_mpp_back);
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#endif
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return slave;
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}
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void spi_free_slave(struct spi_slave *slave)
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{
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#ifdef CONFIG_KIRKWOOD
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kirkwood_mpp_conf(cs_spi_mpp_back, NULL);
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#endif
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free(slave);
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}
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#if defined(CONFIG_SYS_KW_SPI_MPP)
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u32 spi_mpp_backup[4];
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#endif
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__attribute__((weak)) int board_spi_claim_bus(struct spi_slave *slave)
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{
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return 0;
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}
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int spi_claim_bus(struct spi_slave *slave)
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{
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#if defined(CONFIG_SYS_KW_SPI_MPP)
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u32 config;
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u32 spi_mpp_config[4];
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config = CONFIG_SYS_KW_SPI_MPP;
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if (config & MOSI_MPP6)
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spi_mpp_config[0] = MPP6_SPI_MOSI;
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else
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spi_mpp_config[0] = MPP1_SPI_MOSI;
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if (config & SCK_MPP10)
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spi_mpp_config[1] = MPP10_SPI_SCK;
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else
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spi_mpp_config[1] = MPP2_SPI_SCK;
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if (config & MISO_MPP11)
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spi_mpp_config[2] = MPP11_SPI_MISO;
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else
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spi_mpp_config[2] = MPP3_SPI_MISO;
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spi_mpp_config[3] = 0;
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spi_mpp_backup[3] = 0;
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/* set new spi mpp and save current mpp config */
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kirkwood_mpp_conf(spi_mpp_config, spi_mpp_backup);
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#endif
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return board_spi_claim_bus(slave);
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}
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__attribute__((weak)) void board_spi_release_bus(struct spi_slave *slave)
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{
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}
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void spi_release_bus(struct spi_slave *slave)
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{
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#if defined(CONFIG_SYS_KW_SPI_MPP)
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kirkwood_mpp_conf(spi_mpp_backup, NULL);
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#endif
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board_spi_release_bus(slave);
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}
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#ifndef CONFIG_SPI_CS_IS_VALID
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/*
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* you can define this function board specific
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* define above CONFIG in board specific config file and
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* provide the function in board specific src file
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*/
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int spi_cs_is_valid(unsigned int bus, unsigned int cs)
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{
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return bus == 0 && (cs == 0 || cs == 1);
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}
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#endif
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void spi_init(void)
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{
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}
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void spi_cs_activate(struct spi_slave *slave)
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{
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setbits_le32(&spireg->ctrl, KWSPI_CSN_ACT);
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}
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void spi_cs_deactivate(struct spi_slave *slave)
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{
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clrbits_le32(&spireg->ctrl, KWSPI_CSN_ACT);
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}
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int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
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void *din, unsigned long flags)
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{
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unsigned int tmpdout, tmpdin;
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int tm, isread = 0;
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debug("spi_xfer: slave %u:%u dout %p din %p bitlen %u\n",
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slave->bus, slave->cs, dout, din, bitlen);
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if (flags & SPI_XFER_BEGIN)
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spi_cs_activate(slave);
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/*
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* handle data in 8-bit chunks
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* TBD: 2byte xfer mode to be enabled
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*/
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clrsetbits_le32(&spireg->cfg, KWSPI_XFERLEN_MASK, KWSPI_XFERLEN_1BYTE);
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while (bitlen > 4) {
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debug("loopstart bitlen %d\n", bitlen);
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tmpdout = 0;
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/* Shift data so it's msb-justified */
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if (dout)
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tmpdout = *(u32 *)dout & 0xff;
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clrbits_le32(&spireg->irq_cause, KWSPI_SMEMRDIRQ);
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writel(tmpdout, &spireg->dout); /* Write the data out */
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debug("*** spi_xfer: ... %08x written, bitlen %d\n",
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tmpdout, bitlen);
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/*
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* Wait for SPI transmit to get out
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* or time out (1 second = 1000 ms)
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* The NE event must be read and cleared first
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*/
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for (tm = 0, isread = 0; tm < KWSPI_TIMEOUT; ++tm) {
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if (readl(&spireg->irq_cause) & KWSPI_SMEMRDIRQ) {
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isread = 1;
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tmpdin = readl(&spireg->din);
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debug("spi_xfer: din %p..%08x read\n",
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din, tmpdin);
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if (din) {
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*((u8 *)din) = (u8)tmpdin;
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din += 1;
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}
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if (dout)
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dout += 1;
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bitlen -= 8;
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}
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if (isread)
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break;
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}
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if (tm >= KWSPI_TIMEOUT)
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printf("*** spi_xfer: Time out during SPI transfer\n");
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debug("loopend bitlen %d\n", bitlen);
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}
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if (flags & SPI_XFER_END)
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spi_cs_deactivate(slave);
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return 0;
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}
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