upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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372 lines
15 KiB
372 lines
15 KiB
/*
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* (C) Copyright 2009-2010
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* Stefan Roese, DENX Software Engineering, sr@denx.de.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/ppc4xx.h>
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#include <i2c.h>
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#include <libfdt.h>
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#include <fdt_support.h>
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#include <netdev.h>
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#include <asm/processor.h>
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#include <asm/io.h>
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#include <asm/ppc4xx-gpio.h>
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#include <asm/4xx_pcie.h>
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#include <asm/errno.h>
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#include <asm/mmu.h>
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DECLARE_GLOBAL_DATA_PTR;
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int board_early_init_f(void)
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{
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unsigned long mfr;
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/*
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* Interrupt controller setup for the ICON 440SPe board.
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*
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*--------------------------------------------------------------------
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* IRQ | Source | Pol. | Sensi.| Crit.
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*--------+-----------------------------------+-------+-------+-------
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* IRQ 00 | UART0 | High | Level | Non
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* IRQ 01 | UART1 | High | Level | Non
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* IRQ 02 | IIC0 | High | Level | Non
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* IRQ 03 | IIC1 | High | Level | Non
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* IRQ 04 | PCI0X0 MSG IN | High | Level | Non
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* IRQ 05 | PCI0X0 CMD Write | High | Level | Non
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* IRQ 06 | PCI0X0 Power Mgt | High | Level | Non
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* IRQ 07 | PCI0X0 VPD Access | Rising| Edge | Non
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* IRQ 08 | PCI0X0 MSI level 0 | High | Lvl/ed| Non
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* IRQ 09 | External IRQ 15 - (PCI-Express) | pgm H | Pgm | Non
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* IRQ 10 | UIC2 Non-critical Int. | NA | NA | Non
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* IRQ 11 | UIC2 Critical Interrupt | NA | NA | Crit
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* IRQ 12 | PCI Express MSI Level 0 | Rising| Edge | Non
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* IRQ 13 | PCI Express MSI Level 1 | Rising| Edge | Non
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* IRQ 14 | PCI Express MSI Level 2 | Rising| Edge | Non
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* IRQ 15 | PCI Express MSI Level 3 | Rising| Edge | Non
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* IRQ 16 | UIC3 Non-critical Int. | NA | NA | Non
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* IRQ 17 | UIC3 Critical Interrupt | NA | NA | Crit
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* IRQ 18 | External IRQ 14 - (PCI-Express) | Pgm | Pgm | Non
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* IRQ 19 | DMA Channel 0 FIFO Full | High | Level | Non
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* IRQ 20 | DMA Channel 0 Stat FIFO | High | Level | Non
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* IRQ 21 | DMA Channel 1 FIFO Full | High | Level | Non
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* IRQ 22 | DMA Channel 1 Stat FIFO | High | Level | Non
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* IRQ 23 | I2O Inbound Doorbell | High | Level | Non
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* IRQ 24 | Inbound Post List FIFO Not Empt | High | Level | Non
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* IRQ 25 | I2O Region 0 LL PLB Write | High | Level | Non
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* IRQ 26 | I2O Region 1 LL PLB Write | High | Level | Non
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* IRQ 27 | I2O Region 0 HB PLB Write | High | Level | Non
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* IRQ 28 | I2O Region 1 HB PLB Write | High | Level | Non
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* IRQ 29 | GPT Down Count Timer | Rising| Edge | Non
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* IRQ 30 | UIC1 Non-critical Int. | NA | NA | Non
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* IRQ 31 | UIC1 Critical Interrupt | NA | NA | Crit.
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*--------------------------------------------------------------------
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* IRQ 32 | Ext. IRQ 13 - (PCI-Express) |pgm (H)|pgm/Lvl| Non
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* IRQ 33 | MAL Serr | High | Level | Non
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* IRQ 34 | MAL Txde | High | Level | Non
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* IRQ 35 | MAL Rxde | High | Level | Non
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* IRQ 36 | DMC CE or DMC UE | High | Level | Non
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* IRQ 37 | EBC or UART2 | High |Lvl Edg| Non
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* IRQ 38 | MAL TX EOB | High | Level | Non
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* IRQ 39 | MAL RX EOB | High | Level | Non
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* IRQ 40 | PCIX0 MSI Level 1 | High |Lvl Edg| Non
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* IRQ 41 | PCIX0 MSI level 2 | High |Lvl Edg| Non
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* IRQ 42 | PCIX0 MSI level 3 | High |Lvl Edg| Non
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* IRQ 43 | L2 Cache | Risin | Edge | Non
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* IRQ 44 | GPT Compare Timer 0 | Risin | Edge | Non
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* IRQ 45 | GPT Compare Timer 1 | Risin | Edge | Non
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* IRQ 46 | GPT Compare Timer 2 | Risin | Edge | Non
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* IRQ 47 | GPT Compare Timer 3 | Risin | Edge | Non
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* IRQ 48 | GPT Compare Timer 4 | Risin | Edge | Non
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* IRQ 49 | Ext. IRQ 12 - PCI-X |pgm/Fal|pgm/Lvl| Non
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* IRQ 50 | Ext. IRQ 11 - |pgm (H)|pgm/Lvl| Non
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* IRQ 51 | Ext. IRQ 10 - |pgm (H)|pgm/Lvl| Non
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* IRQ 52 | Ext. IRQ 9 |pgm (H)|pgm/Lvl| Non
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* IRQ 53 | Ext. IRQ 8 |pgm (H)|pgm/Lvl| Non
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* IRQ 54 | DMA Error | High | Level | Non
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* IRQ 55 | DMA I2O Error | High | Level | Non
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* IRQ 56 | Serial ROM | High | Level | Non
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* IRQ 57 | PCIX0 Error | High | Edge | Non
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* IRQ 58 | Ext. IRQ 7- |pgm (H)|pgm/Lvl| Non
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* IRQ 59 | Ext. IRQ 6- |pgm (H)|pgm/Lvl| Non
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* IRQ 60 | EMAC0 Interrupt | High | Level | Non
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* IRQ 61 | EMAC0 Wake-up | High | Level | Non
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* IRQ 62 | Reserved | High | Level | Non
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* IRQ 63 | XOR | High | Level | Non
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*--------------------------------------------------------------------
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* IRQ 64 | PE0 AL | High | Level | Non
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* IRQ 65 | PE0 VPD Access | Risin | Edge | Non
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* IRQ 66 | PE0 Hot Reset Request | Risin | Edge | Non
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* IRQ 67 | PE0 Hot Reset Request | Falli | Edge | Non
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* IRQ 68 | PE0 TCR | High | Level | Non
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* IRQ 69 | PE0 BusMaster VCO | Falli | Edge | Non
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* IRQ 70 | PE0 DCR Error | High | Level | Non
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* IRQ 71 | Reserved | N/A | N/A | Non
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* IRQ 72 | PE1 AL | High | Level | Non
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* IRQ 73 | PE1 VPD Access | Risin | Edge | Non
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* IRQ 74 | PE1 Hot Reset Request | Risin | Edge | Non
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* IRQ 75 | PE1 Hot Reset Request | Falli | Edge | Non
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* IRQ 76 | PE1 TCR | High | Level | Non
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* IRQ 77 | PE1 BusMaster VCO | Falli | Edge | Non
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* IRQ 78 | PE1 DCR Error | High | Level | Non
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* IRQ 79 | Reserved | N/A | N/A | Non
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* IRQ 80 | PE2 AL | High | Level | Non
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* IRQ 81 | PE2 VPD Access | Risin | Edge | Non
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* IRQ 82 | PE2 Hot Reset Request | Risin | Edge | Non
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* IRQ 83 | PE2 Hot Reset Request | Falli | Edge | Non
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* IRQ 84 | PE2 TCR | High | Level | Non
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* IRQ 85 | PE2 BusMaster VCO | Falli | Edge | Non
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* IRQ 86 | PE2 DCR Error | High | Level | Non
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* IRQ 87 | Reserved | N/A | N/A | Non
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* IRQ 88 | External IRQ(5) | Progr | Progr | Non
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* IRQ 89 | External IRQ 4 - Ethernet | Progr | Progr | Non
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* IRQ 90 | External IRQ 3 - PCI-X | Progr | Progr | Non
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* IRQ 91 | External IRQ 2 - PCI-X | Progr | Progr | Non
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* IRQ 92 | External IRQ 1 - PCI-X | Progr | Progr | Non
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* IRQ 93 | External IRQ 0 - PCI-X | Progr | Progr | Non
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* IRQ 94 | Reserved | N/A | N/A | Non
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* IRQ 95 | Reserved | N/A | N/A | Non
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*--------------------------------------------------------------------
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* IRQ 96 | PE0 INTA | High | Level | Non
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* IRQ 97 | PE0 INTB | High | Level | Non
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* IRQ 98 | PE0 INTC | High | Level | Non
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* IRQ 99 | PE0 INTD | High | Level | Non
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* IRQ 100| PE1 INTA | High | Level | Non
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* IRQ 101| PE1 INTB | High | Level | Non
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* IRQ 102| PE1 INTC | High | Level | Non
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* IRQ 103| PE1 INTD | High | Level | Non
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* IRQ 104| PE2 INTA | High | Level | Non
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* IRQ 105| PE2 INTB | High | Level | Non
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* IRQ 106| PE2 INTC | High | Level | Non
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* IRQ 107| PE2 INTD | Risin | Edge | Non
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* IRQ 108| PCI Express MSI Level 4 | Risin | Edge | Non
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* IRQ 109| PCI Express MSI Level 5 | Risin | Edge | Non
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* IRQ 110| PCI Express MSI Level 6 | Risin | Edge | Non
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* IRQ 111| PCI Express MSI Level 7 | Risin | Edge | Non
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* IRQ 116| PCI Express MSI Level 12 | Risin | Edge | Non
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* IRQ 112| PCI Express MSI Level 8 | Risin | Edge | Non
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* IRQ 113| PCI Express MSI Level 9 | Risin | Edge | Non
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* IRQ 114| PCI Express MSI Level 10 | Risin | Edge | Non
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* IRQ 115| PCI Express MSI Level 11 | Risin | Edge | Non
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* IRQ 117| PCI Express MSI Level 13 | Risin | Edge | Non
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* IRQ 118| PCI Express MSI Level 14 | Risin | Edge | Non
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* IRQ 119| PCI Express MSI Level 15 | Risin | Edge | Non
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* IRQ 120| PCI Express MSI Level 16 | Risin | Edge | Non
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* IRQ 121| PCI Express MSI Level 17 | Risin | Edge | Non
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* IRQ 122| PCI Express MSI Level 18 | Risin | Edge | Non
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* IRQ 123| PCI Express MSI Level 19 | Risin | Edge | Non
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* IRQ 124| PCI Express MSI Level 20 | Risin | Edge | Non
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* IRQ 125| PCI Express MSI Level 21 | Risin | Edge | Non
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* IRQ 126| PCI Express MSI Level 22 | Risin | Edge | Non
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* IRQ 127| PCI Express MSI Level 23 | Risin | Edge | Non
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*/
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/*
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* Put UICs in PowerPC 440SPe mode.
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* Initialise UIC registers. Clear all interrupts. Disable all
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* interrupts. Set critical interrupt values. Set interrupt polarities.
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* Set interrupt trigger levels. Make bit 0 High priority. Clear all
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* interrupts again.
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*/
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mtdcr(UIC3SR, 0xffffffff); /* Clear all interrupts */
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mtdcr(UIC3ER, 0x00000000); /* disable all interrupts */
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mtdcr(UIC3CR, 0x00000000); /* Set Critical / Non Critical IRQs */
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mtdcr(UIC3PR, 0xffffffff); /* Set Interrupt Polarities*/
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mtdcr(UIC3TR, 0x001fffff); /* Set Interrupt Trigger Levels */
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mtdcr(UIC3VR, 0x00000001); /* Set Vect base=0,INT31 Highest prio */
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mtdcr(UIC3SR, 0x00000000); /* clear all interrupts*/
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mtdcr(UIC3SR, 0xffffffff); /* clear all interrupts*/
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mtdcr(UIC2SR, 0xffffffff); /* Clear all interrupts */
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mtdcr(UIC2ER, 0x00000000); /* disable all interrupts*/
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mtdcr(UIC2CR, 0x00000000); /* Set Critical / Non Critical IRQs */
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mtdcr(UIC2PR, 0xebebebff); /* Set Interrupt Polarities*/
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mtdcr(UIC2TR, 0x74747400); /* Set Interrupt Trigger Levels */
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mtdcr(UIC2VR, 0x00000001); /* Set Vect base=0,INT31 Highest prio */
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mtdcr(UIC2SR, 0x00000000); /* clear all interrupts */
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mtdcr(UIC2SR, 0xffffffff); /* clear all interrupts */
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mtdcr(UIC1SR, 0xffffffff); /* Clear all interrupts*/
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mtdcr(UIC1ER, 0x00000000); /* disable all interrupts*/
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mtdcr(UIC1CR, 0x00000000); /* Set Critical / Non Critical IRQs */
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mtdcr(UIC1PR, 0xffffffff); /* Set Interrupt Polarities */
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mtdcr(UIC1TR, 0x001f8040); /* Set Interrupt Trigger Levels*/
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mtdcr(UIC1VR, 0x00000001); /* Set Vect base=0,INT31 Highest prio */
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mtdcr(UIC1SR, 0x00000000); /* clear all interrupts*/
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mtdcr(UIC1SR, 0xffffffff); /* clear all interrupts*/
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mtdcr(UIC0SR, 0xffffffff); /* Clear all interrupts */
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mtdcr(UIC0ER, 0x00000000); /* disable all int. excepted cascade */
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mtdcr(UIC0CR, 0x00104001); /* Set Critical / Non Critical IRQs */
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mtdcr(UIC0PR, 0xffffffff); /* Set Interrupt Polarities*/
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mtdcr(UIC0TR, 0x010f0004); /* Set Interrupt Trigger Levels */
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mtdcr(UIC0VR, 0x00000001); /* Set Vect base=0,INT31 Highest prio */
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mtdcr(UIC0SR, 0x00000000); /* clear all interrupts*/
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mtdcr(UIC0SR, 0xffffffff); /* clear all interrupts*/
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mfsdr(SDR0_MFR, mfr);
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mfr |= SDR0_MFR_FIXD; /* Workaround for PCI/DMA */
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mtsdr(SDR0_MFR, mfr);
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mtsdr(SDR0_PFC0, CONFIG_SYS_PFC0);
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out_be32((void *)GPIO0_OR, CONFIG_SYS_GPIO_OR);
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out_be32((void *)GPIO0_ODR, CONFIG_SYS_GPIO_ODR);
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out_be32((void *)GPIO0_TCR, CONFIG_SYS_GPIO_TCR);
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return 0;
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}
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int board_early_init_r(void)
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{
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/*
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* ICON has 64MBytes of NOR FLASH (Spansion 29GL512), but the
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* boot EBC mapping only supports a maximum of 16MBytes
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* (4.ff00.0000 - 4.ffff.ffff).
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* To solve this problem, the FLASH has to get remapped to another
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* EBC address which accepts bigger regions:
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*
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* 0xfc00.0000 -> 4.ec00.0000
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*/
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/* Remap the NOR FLASH to 0xec00.0000 ... 0xefff.ffff */
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mtebc(PB0CR, CONFIG_SYS_FLASH_BASE_PHYS_L | 0xda000);
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/* Remove TLB entry of boot EBC mapping */
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remove_tlb(CONFIG_SYS_BOOT_BASE_ADDR, 16 << 20);
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/* Add TLB entry for 0xfc00.0000 -> 0x4.ec00.0000 */
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program_tlb(CONFIG_SYS_FLASH_BASE_PHYS, CONFIG_SYS_FLASH_BASE,
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CONFIG_SYS_FLASH_SIZE, TLB_WORD2_I_ENABLE);
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/*
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* Now accessing of the whole 64Mbytes of NOR FLASH at virtual address
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* 0xfc00.0000 is possible
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*/
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/*
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* Clear potential errors resulting from auto-calibration.
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* If not done, then we could get an interrupt later on when
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* exceptions are enabled.
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*/
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set_mcsr(get_mcsr());
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return 0;
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}
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int checkboard(void)
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{
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char buf[64];
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int i = getenv_f("serial#", buf, sizeof(buf));
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printf("Board: ICON");
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if (i > 0) {
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puts(", serial# ");
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puts(buf);
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}
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putc('\n');
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return 0;
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}
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/*
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* Override the default functions in cpu/ppc4xx/44x_spd_ddr2.c with
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* board specific values.
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*
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* Tested successfully with the following SODIMM:
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* Crucial CT6464AC667.4FE - 512MB SO-DIMM (single rank)
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*
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* Tests with Micron MT4HTF6464HZ-667H1 showed problems in "cold" state,
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* directly after power-up. Only after running for more than 10 minutes
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* real stable auto-calibration windows could be found.
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*/
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u32 ddr_wrdtr(u32 default_val)
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{
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return SDRAM_WRDTR_LLWP_1_CYC | SDRAM_WRDTR_WTR_90_DEG_ADV;
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}
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u32 ddr_clktr(u32 default_val)
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{
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return SDRAM_CLKTR_CLKP_180_DEG_ADV;
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}
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/*
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* Override the weak default implementation and return the
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* last PCIe slot number (max number - 1).
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*/
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int board_pcie_last(void)
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{
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/* Only 2 PCIe ports used on ICON, so the last one is 1 */
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return 1;
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}
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/*
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* Video
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*/
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#ifdef CONFIG_VIDEO_SM501
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#include <sm501.h>
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#define DISPLAY_WIDTH 640
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#define DISPLAY_HEIGHT 480
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static const SMI_REGS sm502_init_regs[] = {
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{0x00004, 0x0},
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{0x00040, 0x00021847},
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{0x00044, 0x091a0a01}, /* 24 MHz pixclk */
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{0x00054, 0x0},
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{0x00048, 0x00021847},
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{0x0004C, 0x091a0a01},
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{0x00054, 0x1},
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{0x80004, 0xc428bb17},
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{0x8000C, 0x00000000},
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{0x80010, 0x0a000a00},
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{0x80014, 0x02800000},
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{0x80018, 0x01e00000},
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{0x8001C, 0x00000000},
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{0x80020, 0x01e00280},
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{0x80024, 0x02fa027f},
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{0x80028, 0x004a0280},
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{0x8002C, 0x020c01df},
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{0x80030, 0x000201e7},
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{0x80200, 0x00010000},
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{0x00008, 0x20000000}, /* gpio29 is pwm0, LED_PWM */
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{0x0000C, 0x3f000000}, /* gpio56 - gpio61 as flat panel data pins */
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{0x10020, 0x25725728}, /* 20 kHz pwm0, 50 % duty cycle, disabled */
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{0x80000, 0x0f010106}, /* vsync & hsync pos, disp on */
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{0, 0}
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};
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/*
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* Return a pointer to the register initialization table.
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*/
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const SMI_REGS *board_get_regs(void)
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{
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return sm502_init_regs;
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}
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int board_get_width(void)
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{
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return DISPLAY_WIDTH;
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}
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int board_get_height(void)
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{
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return DISPLAY_HEIGHT;
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}
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#ifdef CONFIG_CONSOLE_EXTRA_INFO
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/*
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* Return text to be printed besides the logo.
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*/
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void video_get_info_str(int line_number, char *info)
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{
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if (line_number == 1)
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strcpy(info, " Board: ICON");
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else
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info[0] = '\0';
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}
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#endif
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#endif /* CONFIG_VIDEO_SM501 */
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