upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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288 lines
7.7 KiB
288 lines
7.7 KiB
/*
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* (C) Copyright 2006
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* Sylvie Gohl, AMCC/IBM, gohl.sylvie@fr.ibm.com
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* Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
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* Thierry Roman, AMCC/IBM, thierry_roman@fr.ibm.com
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* Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com
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* Robert Snyder, AMCC/IBM, rob.snyder@fr.ibm.com
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*
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* (C) Copyright 2007-2008
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* Stefan Roese, DENX Software Engineering, sr@denx.de.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/* define DEBUG for debugging output (obviously ;-)) */
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#if 0
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#define DEBUG
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#endif
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#include <common.h>
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#include <asm/processor.h>
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#include <asm/mmu.h>
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#include <asm/io.h>
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#include <asm/cache.h>
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#include <ppc440.h>
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#include <watchdog.h>
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/*
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* This DDR2 setup code can dynamically setup the TLB entries for the DDR2 memory
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* region. Right now the cache should still be disabled in U-Boot because of the
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* EMAC driver, that need it's buffer descriptor to be located in non cached
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* memory.
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*
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* If at some time this restriction doesn't apply anymore, just define
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* CFG_ENABLE_SDRAM_CACHE in the board config file and this code should setup
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* everything correctly.
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*/
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#ifdef CFG_ENABLE_SDRAM_CACHE
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#define MY_TLB_WORD2_I_ENABLE 0 /* enable caching on SDRAM */
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#else
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#define MY_TLB_WORD2_I_ENABLE TLB_WORD2_I_ENABLE /* disable caching on SDRAM */
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#endif
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/*-----------------------------------------------------------------------------+
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* Prototypes
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*-----------------------------------------------------------------------------*/
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extern int denali_wait_for_dlllock(void);
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extern void denali_core_search_data_eye(void);
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extern void dcbz_area(u32 start_address, u32 num_bytes);
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static u32 is_ecc_enabled(void)
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{
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u32 val;
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mfsdram(DDR0_22, val);
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val &= DDR0_22_CTRL_RAW_MASK;
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if (val)
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return 1;
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else
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return 0;
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}
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void board_add_ram_info(int use_default)
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{
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PPC4xx_SYS_INFO board_cfg;
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u32 val;
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if (is_ecc_enabled())
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puts(" (ECC");
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else
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puts(" (ECC not");
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get_sys_info(&board_cfg);
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printf(" enabled, %ld MHz", (board_cfg.freqPLB * 2) / 1000000);
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mfsdram(DDR0_03, val);
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val = DDR0_03_CASLAT_DECODE(val);
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printf(", CL%d)", val);
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}
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#ifdef CONFIG_DDR_ECC
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static void wait_ddr_idle(void)
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{
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/*
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* Controller idle status cannot be determined for Denali
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* DDR2 code. Just return here.
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*/
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}
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static void program_ecc(u32 start_address,
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u32 num_bytes,
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u32 tlb_word2_i_value)
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{
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u32 val;
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u32 current_addr = start_address;
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u32 size;
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int bytes_remaining;
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sync();
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wait_ddr_idle();
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/*
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* Because of 440EPx errata CHIP 11, we don't touch the last 256
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* bytes of SDRAM.
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*/
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bytes_remaining = num_bytes - CFG_MEM_TOP_HIDE;
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/*
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* We have to write the ECC bytes by zeroing and flushing in smaller
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* steps, since the whole 256MByte takes too long for the external
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* watchdog.
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*/
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while (bytes_remaining > 0) {
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size = min((64 << 20), bytes_remaining);
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/* Write zero's to SDRAM */
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dcbz_area(current_addr, size);
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/* Write modified dcache lines back to memory */
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clean_dcache_range(current_addr, current_addr + size);
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current_addr += 64 << 20;
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bytes_remaining -= 64 << 20;
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WATCHDOG_RESET();
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}
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sync();
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wait_ddr_idle();
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/* Clear error status */
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mfsdram(DDR0_00, val);
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mtsdram(DDR0_00, val | DDR0_00_INT_ACK_ALL);
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/* Set 'int_mask' parameter to functionnal value */
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mfsdram(DDR0_01, val);
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mtsdram(DDR0_01, ((val &~ DDR0_01_INT_MASK_MASK) | DDR0_01_INT_MASK_ALL_OFF));
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sync();
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wait_ddr_idle();
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}
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#endif
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/*************************************************************************
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*
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* initdram -- 440EPx's DDR controller is a DENALI Core
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*
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************************************************************************/
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phys_size_t initdram (int board_type)
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{
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#if 0 /* test-only: will remove this define later, when ECC problems are solved! */
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/* CL=3 */
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mtsdram(DDR0_02, 0x00000000);
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mtsdram(DDR0_00, 0x0000190A);
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mtsdram(DDR0_01, 0x01000000);
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mtsdram(DDR0_03, 0x02030603); /* A suitable burst length was taken. CAS is right for our board */
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mtsdram(DDR0_04, 0x0A030300);
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mtsdram(DDR0_05, 0x02020308);
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mtsdram(DDR0_06, 0x0103C812);
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mtsdram(DDR0_07, 0x00090100);
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mtsdram(DDR0_08, 0x02c80001);
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mtsdram(DDR0_09, 0x00011D5F);
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mtsdram(DDR0_10, 0x00000300);
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mtsdram(DDR0_11, 0x000CC800);
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mtsdram(DDR0_12, 0x00000003);
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mtsdram(DDR0_14, 0x00000000);
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mtsdram(DDR0_17, 0x1e000000);
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mtsdram(DDR0_18, 0x1e1e1e1e);
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mtsdram(DDR0_19, 0x1e1e1e1e);
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mtsdram(DDR0_20, 0x0B0B0B0B);
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mtsdram(DDR0_21, 0x0B0B0B0B);
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#ifdef CONFIG_DDR_ECC
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mtsdram(DDR0_22, 0x00267F0B | DDR0_22_CTRL_RAW_ECC_ENABLE); /* enable ECC */
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#else
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mtsdram(DDR0_22, 0x00267F0B);
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#endif
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mtsdram(DDR0_23, 0x01000000);
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mtsdram(DDR0_24, 0x01010001);
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mtsdram(DDR0_26, 0x2D93028A);
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mtsdram(DDR0_27, 0x0784682B);
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mtsdram(DDR0_28, 0x00000080);
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mtsdram(DDR0_31, 0x00000000);
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mtsdram(DDR0_42, 0x01000006);
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mtsdram(DDR0_43, 0x030A0200);
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mtsdram(DDR0_44, 0x00000003);
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mtsdram(DDR0_02, 0x00000001); /* Activate the denali core */
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#else
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/* CL=4 */
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mtsdram(DDR0_02, 0x00000000);
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mtsdram(DDR0_00, 0x0000190A);
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mtsdram(DDR0_01, 0x01000000);
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mtsdram(DDR0_03, 0x02040803); /* A suitable burst length was taken. CAS is right for our board */
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mtsdram(DDR0_04, 0x0B030300);
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mtsdram(DDR0_05, 0x02020308);
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mtsdram(DDR0_06, 0x0003C812);
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mtsdram(DDR0_07, 0x00090100);
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mtsdram(DDR0_08, 0x03c80001);
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mtsdram(DDR0_09, 0x00011D5F);
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mtsdram(DDR0_10, 0x00000300);
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mtsdram(DDR0_11, 0x000CC800);
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mtsdram(DDR0_12, 0x00000003);
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mtsdram(DDR0_14, 0x00000000);
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mtsdram(DDR0_17, 0x1e000000);
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mtsdram(DDR0_18, 0x1e1e1e1e);
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mtsdram(DDR0_19, 0x1e1e1e1e);
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mtsdram(DDR0_20, 0x0B0B0B0B);
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mtsdram(DDR0_21, 0x0B0B0B0B);
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#ifdef CONFIG_DDR_ECC
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mtsdram(DDR0_22, 0x00267F0B | DDR0_22_CTRL_RAW_ECC_ENABLE); /* enable ECC */
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#else
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mtsdram(DDR0_22, 0x00267F0B);
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#endif
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mtsdram(DDR0_23, 0x01000000);
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mtsdram(DDR0_24, 0x01010001);
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mtsdram(DDR0_26, 0x2D93028A);
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mtsdram(DDR0_27, 0x0784682B);
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mtsdram(DDR0_28, 0x00000080);
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mtsdram(DDR0_31, 0x00000000);
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mtsdram(DDR0_42, 0x01000008);
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mtsdram(DDR0_43, 0x050A0200);
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mtsdram(DDR0_44, 0x00000005);
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mtsdram(DDR0_02, 0x00000001); /* Activate the denali core */
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#endif
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denali_wait_for_dlllock();
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#if defined(CONFIG_DDR_DATA_EYE)
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/* -----------------------------------------------------------+
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* Perform data eye search if requested.
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* ----------------------------------------------------------*/
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program_tlb(0, CFG_SDRAM_BASE, CFG_MBYTES_SDRAM << 20,
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TLB_WORD2_I_ENABLE);
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denali_core_search_data_eye();
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remove_tlb(CFG_SDRAM_BASE, CFG_MBYTES_SDRAM << 20);
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#endif
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/*
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* Program tlb entries for this size (dynamic)
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*/
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program_tlb(0, CFG_SDRAM_BASE, CFG_MBYTES_SDRAM << 20,
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MY_TLB_WORD2_I_ENABLE);
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/*
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* Setup 2nd TLB with same physical address but different virtual address
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* with cache enabled. This is done for fast ECC generation.
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*/
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program_tlb(0, CFG_DDR_CACHED_ADDR, CFG_MBYTES_SDRAM << 20, 0);
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#ifdef CONFIG_DDR_ECC
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/*
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* If ECC is enabled, initialize the parity bits.
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*/
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program_ecc(CFG_DDR_CACHED_ADDR, CFG_MBYTES_SDRAM << 20, 0);
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#endif
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/*
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* Clear possible errors resulting from data-eye-search.
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* If not done, then we could get an interrupt later on when
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* exceptions are enabled.
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*/
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set_mcsr(get_mcsr());
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return (CFG_MBYTES_SDRAM << 20);
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}
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