upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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289 lines
7.9 KiB
289 lines
7.9 KiB
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Microchip PIC32 MUSB "glue layer"
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*
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* Copyright (C) 2015, Microchip Technology Inc.
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* Cristian Birsan <cristian.birsan@microchip.com>
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* Purna Chandra Mandal <purna.mandal@microchip.com>
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*
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* Based on the dsps "glue layer" code.
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*/
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#include <common.h>
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#include <linux/usb/musb.h>
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#include "linux-compat.h"
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#include "musb_core.h"
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#include "musb_uboot.h"
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DECLARE_GLOBAL_DATA_PTR;
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#define PIC32_TX_EP_MASK 0x0f /* EP0 + 7 Tx EPs */
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#define PIC32_RX_EP_MASK 0x0e /* 7 Rx EPs */
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#define MUSB_SOFTRST 0x7f
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#define MUSB_SOFTRST_NRST BIT(0)
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#define MUSB_SOFTRST_NRSTX BIT(1)
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#define USBCRCON 0
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#define USBCRCON_USBWKUPEN BIT(0) /* Enable Wakeup Interrupt */
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#define USBCRCON_USBRIE BIT(1) /* Enable Remote resume Interrupt */
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#define USBCRCON_USBIE BIT(2) /* Enable USB General interrupt */
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#define USBCRCON_SENDMONEN BIT(3) /* Enable Session End VBUS monitoring */
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#define USBCRCON_BSVALMONEN BIT(4) /* Enable B-Device VBUS monitoring */
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#define USBCRCON_ASVALMONEN BIT(5) /* Enable A-Device VBUS monitoring */
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#define USBCRCON_VBUSMONEN BIT(6) /* Enable VBUS monitoring */
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#define USBCRCON_PHYIDEN BIT(7) /* PHY ID monitoring enable */
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#define USBCRCON_USBIDVAL BIT(8) /* USB ID value */
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#define USBCRCON_USBIDOVEN BIT(9) /* USB ID override enable */
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#define USBCRCON_USBWK BIT(24) /* USB Wakeup Status */
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#define USBCRCON_USBRF BIT(25) /* USB Resume Status */
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#define USBCRCON_USBIF BIT(26) /* USB General Interrupt Status */
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/* PIC32 controller data */
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struct pic32_musb_data {
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struct musb_host_data mdata;
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struct device dev;
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void __iomem *musb_glue;
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};
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#define to_pic32_musb_data(d) \
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container_of(d, struct pic32_musb_data, dev)
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static void pic32_musb_disable(struct musb *musb)
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{
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/* no way to shut the controller */
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}
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static int pic32_musb_enable(struct musb *musb)
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{
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/* soft reset by NRSTx */
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musb_writeb(musb->mregs, MUSB_SOFTRST, MUSB_SOFTRST_NRSTX);
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/* set mode */
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musb_platform_set_mode(musb, musb->board_mode);
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return 0;
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}
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static irqreturn_t pic32_interrupt(int irq, void *hci)
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{
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struct musb *musb = hci;
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irqreturn_t ret = IRQ_NONE;
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u32 epintr, usbintr;
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/* ack usb core interrupts */
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musb->int_usb = musb_readb(musb->mregs, MUSB_INTRUSB);
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if (musb->int_usb)
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musb_writeb(musb->mregs, MUSB_INTRUSB, musb->int_usb);
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/* ack endpoint interrupts */
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musb->int_rx = musb_readw(musb->mregs, MUSB_INTRRX) & PIC32_RX_EP_MASK;
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if (musb->int_rx)
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musb_writew(musb->mregs, MUSB_INTRRX, musb->int_rx);
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musb->int_tx = musb_readw(musb->mregs, MUSB_INTRTX) & PIC32_TX_EP_MASK;
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if (musb->int_tx)
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musb_writew(musb->mregs, MUSB_INTRTX, musb->int_tx);
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/* drop spurious RX and TX if device is disconnected */
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if (musb->int_usb & MUSB_INTR_DISCONNECT) {
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musb->int_tx = 0;
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musb->int_rx = 0;
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}
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if (musb->int_tx || musb->int_rx || musb->int_usb)
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ret = musb_interrupt(musb);
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return ret;
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}
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static int pic32_musb_set_mode(struct musb *musb, u8 mode)
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{
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struct device *dev = musb->controller;
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struct pic32_musb_data *pdata = to_pic32_musb_data(dev);
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switch (mode) {
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case MUSB_HOST:
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clrsetbits_le32(pdata->musb_glue + USBCRCON,
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USBCRCON_USBIDVAL, USBCRCON_USBIDOVEN);
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break;
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case MUSB_PERIPHERAL:
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setbits_le32(pdata->musb_glue + USBCRCON,
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USBCRCON_USBIDVAL | USBCRCON_USBIDOVEN);
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break;
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case MUSB_OTG:
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dev_err(dev, "support for OTG is unimplemented\n");
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break;
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default:
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dev_err(dev, "unsupported mode %d\n", mode);
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return -EINVAL;
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}
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return 0;
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}
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static int pic32_musb_init(struct musb *musb)
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{
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struct pic32_musb_data *pdata = to_pic32_musb_data(musb->controller);
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u32 ctrl, hwvers;
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u8 power;
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/* Returns zero if not clocked */
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hwvers = musb_read_hwvers(musb->mregs);
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if (!hwvers)
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return -ENODEV;
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/* Reset the musb */
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power = musb_readb(musb->mregs, MUSB_POWER);
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power = power | MUSB_POWER_RESET;
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musb_writeb(musb->mregs, MUSB_POWER, power);
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mdelay(100);
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/* Start the on-chip PHY and its PLL. */
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power = power & ~MUSB_POWER_RESET;
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musb_writeb(musb->mregs, MUSB_POWER, power);
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musb->isr = pic32_interrupt;
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ctrl = USBCRCON_USBIF | USBCRCON_USBRF |
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USBCRCON_USBWK | USBCRCON_USBIDOVEN |
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USBCRCON_PHYIDEN | USBCRCON_USBIE |
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USBCRCON_USBRIE | USBCRCON_USBWKUPEN |
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USBCRCON_VBUSMONEN;
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writel(ctrl, pdata->musb_glue + USBCRCON);
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return 0;
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}
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/* PIC32 supports only 32bit read operation */
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void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
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{
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void __iomem *fifo = hw_ep->fifo;
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u32 val, rem = len % 4;
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/* USB stack ensures dst is always 32bit aligned. */
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readsl(fifo, dst, len / 4);
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if (rem) {
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dst += len & ~0x03;
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val = musb_readl(fifo, 0);
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memcpy(dst, &val, rem);
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}
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}
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const struct musb_platform_ops pic32_musb_ops = {
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.init = pic32_musb_init,
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.set_mode = pic32_musb_set_mode,
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.disable = pic32_musb_disable,
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.enable = pic32_musb_enable,
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};
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/* PIC32 default FIFO config - fits in 8KB */
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static struct musb_fifo_cfg pic32_musb_fifo_config[] = {
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{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
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{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
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{ .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
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{ .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
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{ .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, },
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{ .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, },
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{ .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, },
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{ .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, },
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{ .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, },
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{ .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, },
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{ .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 512, },
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{ .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 512, },
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{ .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 512, },
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{ .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 512, },
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};
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static struct musb_hdrc_config pic32_musb_config = {
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.fifo_cfg = pic32_musb_fifo_config,
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.fifo_cfg_size = ARRAY_SIZE(pic32_musb_fifo_config),
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.multipoint = 1,
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.dyn_fifo = 1,
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.num_eps = 8,
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.ram_bits = 11,
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};
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/* PIC32 has one MUSB controller which can be host or gadget */
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static struct musb_hdrc_platform_data pic32_musb_plat = {
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.mode = MUSB_HOST,
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.config = &pic32_musb_config,
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.power = 250, /* 500mA */
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.platform_ops = &pic32_musb_ops,
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};
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static int musb_usb_probe(struct udevice *dev)
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{
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struct usb_bus_priv *priv = dev_get_uclass_priv(dev);
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struct pic32_musb_data *pdata = dev_get_priv(dev);
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struct musb_host_data *mdata = &pdata->mdata;
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struct fdt_resource mc, glue;
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void *fdt = (void *)gd->fdt_blob;
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int node = dev_of_offset(dev);
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void __iomem *mregs;
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int ret;
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priv->desc_before_addr = true;
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ret = fdt_get_named_resource(fdt, node, "reg", "reg-names",
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"mc", &mc);
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if (ret < 0) {
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printf("pic32-musb: resource \"mc\" not found\n");
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return ret;
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}
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ret = fdt_get_named_resource(fdt, node, "reg", "reg-names",
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"control", &glue);
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if (ret < 0) {
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printf("pic32-musb: resource \"control\" not found\n");
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return ret;
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}
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mregs = ioremap(mc.start, fdt_resource_size(&mc));
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pdata->musb_glue = ioremap(glue.start, fdt_resource_size(&glue));
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/* init controller */
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#ifdef CONFIG_USB_MUSB_HOST
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mdata->host = musb_init_controller(&pic32_musb_plat,
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&pdata->dev, mregs);
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if (!mdata->host)
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return -EIO;
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ret = musb_lowlevel_init(mdata);
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#else
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pic32_musb_plat.mode = MUSB_PERIPHERAL;
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mdata->host = musb_register(&pic32_musb_plat, &pdata->dev, mregs);
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if (!mdata->host)
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return -EIO;
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#endif
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if ((ret == 0) && mdata->host)
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printf("PIC32 MUSB OTG\n");
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return ret;
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}
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static int musb_usb_remove(struct udevice *dev)
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{
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struct pic32_musb_data *pdata = dev_get_priv(dev);
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musb_stop(pdata->mdata.host);
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return 0;
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}
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static const struct udevice_id pic32_musb_ids[] = {
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{ .compatible = "microchip,pic32mzda-usb" },
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{ }
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};
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U_BOOT_DRIVER(usb_musb) = {
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.name = "pic32-musb",
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.id = UCLASS_USB,
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.of_match = pic32_musb_ids,
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.probe = musb_usb_probe,
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.remove = musb_usb_remove,
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#ifdef CONFIG_USB_MUSB_HOST
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.ops = &musb_usb_ops,
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#endif
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.platdata_auto_alloc_size = sizeof(struct usb_platdata),
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.priv_auto_alloc_size = sizeof(struct pic32_musb_data),
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};
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