upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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104 lines
1.7 KiB
104 lines
1.7 KiB
/*
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* Copyright (C) 2011-2015 Panasonic Corporation
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* Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <linux/sizes.h>
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#include <asm/io.h>
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#include <mach/sg-regs.h>
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static inline u32 sg_memconf_val_ch0(unsigned long size, int num)
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{
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int size_mb = size / num;
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u32 ret;
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switch (size_mb) {
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case SZ_64M:
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ret = SG_MEMCONF_CH0_SZ_64M;
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break;
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case SZ_128M:
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ret = SG_MEMCONF_CH0_SZ_128M;
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break;
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case SZ_256M:
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ret = SG_MEMCONF_CH0_SZ_256M;
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break;
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case SZ_512M:
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ret = SG_MEMCONF_CH0_SZ_512M;
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break;
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case SZ_1G:
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ret = SG_MEMCONF_CH0_SZ_1G;
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break;
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default:
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BUG();
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break;
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}
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switch (num) {
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case 1:
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ret |= SG_MEMCONF_CH0_NUM_1;
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break;
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case 2:
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ret |= SG_MEMCONF_CH0_NUM_2;
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break;
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default:
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BUG();
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break;
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}
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return ret;
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}
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static inline u32 sg_memconf_val_ch1(unsigned long size, int num)
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{
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int size_mb = size / num;
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u32 ret;
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switch (size_mb) {
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case SZ_64M:
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ret = SG_MEMCONF_CH1_SZ_64M;
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break;
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case SZ_128M:
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ret = SG_MEMCONF_CH1_SZ_128M;
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break;
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case SZ_256M:
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ret = SG_MEMCONF_CH1_SZ_256M;
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break;
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case SZ_512M:
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ret = SG_MEMCONF_CH1_SZ_512M;
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break;
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case SZ_1G:
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ret = SG_MEMCONF_CH1_SZ_1G;
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break;
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default:
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BUG();
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break;
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}
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switch (num) {
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case 1:
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ret |= SG_MEMCONF_CH1_NUM_1;
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break;
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case 2:
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ret |= SG_MEMCONF_CH1_NUM_2;
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break;
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default:
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BUG();
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break;
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}
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return ret;
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}
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void memconf_init(void)
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{
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u32 tmp;
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/* Set DDR size */
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tmp = sg_memconf_val_ch0(CONFIG_SDRAM0_SIZE, CONFIG_DDR_NUM_CH0);
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tmp |= sg_memconf_val_ch1(CONFIG_SDRAM1_SIZE, CONFIG_DDR_NUM_CH1);
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#if CONFIG_SDRAM0_BASE + CONFIG_SDRAM0_SIZE < CONFIG_SDRAM1_BASE
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tmp |= SG_MEMCONF_SPARSEMEM;
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#endif
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writel(tmp, SG_MEMCONF);
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}
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