upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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173 lines
8.2 KiB
173 lines
8.2 KiB
/* DO NOT EDIT THIS FILE
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* Automatically generated by generate-def-headers.xsl
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* DO NOT EDIT THIS FILE
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*/
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#ifndef __BFIN_DEF_ADSP_BF561_proc__
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#define __BFIN_DEF_ADSP_BF561_proc__
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#include "../mach-common/ADSP-EDN-core_def.h"
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#include "../mach-common/ADSP-EDN-DUAL-CORE-extended_def.h"
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#define SRAM_BASE_ADDR 0xFFE00000
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#define DMEM_CONTROL 0xFFE00004
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#define DCPLB_STATUS 0xFFE00008
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#define DCPLB_FAULT_ADDR 0xFFE0000C
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#define DCPLB_ADDR0 0xFFE00100
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#define DCPLB_ADDR1 0xFFE00104
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#define DCPLB_ADDR2 0xFFE00108
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#define DCPLB_ADDR3 0xFFE0010C
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#define DCPLB_ADDR4 0xFFE00110
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#define DCPLB_ADDR5 0xFFE00114
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#define DCPLB_ADDR6 0xFFE00118
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#define DCPLB_ADDR7 0xFFE0011C
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#define DCPLB_ADDR8 0xFFE00120
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#define DCPLB_ADDR9 0xFFE00124
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#define DCPLB_ADDR10 0xFFE00128
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#define DCPLB_ADDR11 0xFFE0012C
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#define DCPLB_ADDR12 0xFFE00130
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#define DCPLB_ADDR13 0xFFE00134
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#define DCPLB_ADDR14 0xFFE00138
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#define DCPLB_ADDR15 0xFFE0013C
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#define DCPLB_DATA0 0xFFE00200
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#define DCPLB_DATA1 0xFFE00204
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#define DCPLB_DATA2 0xFFE00208
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#define DCPLB_DATA3 0xFFE0020C
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#define DCPLB_DATA4 0xFFE00210
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#define DCPLB_DATA5 0xFFE00214
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#define DCPLB_DATA6 0xFFE00218
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#define DCPLB_DATA7 0xFFE0021C
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#define DCPLB_DATA8 0xFFE00220
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#define DCPLB_DATA9 0xFFE00224
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#define DCPLB_DATA10 0xFFE00228
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#define DCPLB_DATA11 0xFFE0022C
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#define DCPLB_DATA12 0xFFE00230
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#define DCPLB_DATA13 0xFFE00234
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#define DCPLB_DATA14 0xFFE00238
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#define DCPLB_DATA15 0xFFE0023C
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#define DTEST_COMMAND 0xFFE00300
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#define DTEST_DATA0 0xFFE00400
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#define DTEST_DATA1 0xFFE00404
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#define IMEM_CONTROL 0xFFE01004
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#define ICPLB_STATUS 0xFFE01008
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#define ICPLB_FAULT_ADDR 0xFFE0100C
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#define ICPLB_ADDR0 0xFFE01100
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#define ICPLB_ADDR1 0xFFE01104
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#define ICPLB_ADDR2 0xFFE01108
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#define ICPLB_ADDR3 0xFFE0110C
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#define ICPLB_ADDR4 0xFFE01110
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#define ICPLB_ADDR5 0xFFE01114
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#define ICPLB_ADDR6 0xFFE01118
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#define ICPLB_ADDR7 0xFFE0111C
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#define ICPLB_ADDR8 0xFFE01120
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#define ICPLB_ADDR9 0xFFE01124
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#define ICPLB_ADDR10 0xFFE01128
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#define ICPLB_ADDR11 0xFFE0112C
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#define ICPLB_ADDR12 0xFFE01130
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#define ICPLB_ADDR13 0xFFE01134
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#define ICPLB_ADDR14 0xFFE01138
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#define ICPLB_ADDR15 0xFFE0113C
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#define ICPLB_DATA0 0xFFE01200
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#define ICPLB_DATA1 0xFFE01204
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#define ICPLB_DATA2 0xFFE01208
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#define ICPLB_DATA3 0xFFE0120C
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#define ICPLB_DATA4 0xFFE01210
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#define ICPLB_DATA5 0xFFE01214
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#define ICPLB_DATA6 0xFFE01218
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#define ICPLB_DATA7 0xFFE0121C
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#define ICPLB_DATA8 0xFFE01220
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#define ICPLB_DATA9 0xFFE01224
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#define ICPLB_DATA10 0xFFE01228
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#define ICPLB_DATA11 0xFFE0122C
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#define ICPLB_DATA12 0xFFE01230
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#define ICPLB_DATA13 0xFFE01234
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#define ICPLB_DATA14 0xFFE01238
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#define ICPLB_DATA15 0xFFE0123C
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#define ITEST_COMMAND 0xFFE01300
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#define ITEST_DATA0 0xFFE01400
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#define ITEST_DATA1 0xFFE01404
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#define SICA_SWRST 0xFFC00100
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#define SICA_SYSCR 0xFFC00104
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#define SICA_RVECT 0xFFC00108
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#define SICA_IMASK0 0xFFC0010C
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#define SICA_IMASK1 0xFFC00110
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#define SICA_ISR0 0xFFC00114
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#define SICA_ISR1 0xFFC00118
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#define SICA_IWR0 0xFFC0011C
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#define SICA_IWR1 0xFFC00120
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#define SICA_IAR0 0xFFC00124
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#define SICA_IAR1 0xFFC00128
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#define SICA_IAR2 0xFFC0012C
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#define SICA_IAR3 0xFFC00130
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#define SICA_IAR4 0xFFC00134
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#define SICA_IAR5 0xFFC00138
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#define SICA_IAR6 0xFFC0013C
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#define SICA_IAR7 0xFFC00140
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#define SICB_SWRST 0xFFC01100
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#define SICB_SYSCR 0xFFC01104
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#define SICB_RVECT 0xFFC01108
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#define SICB_IMASK0 0xFFC0110C
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#define SICB_IMASK1 0xFFC01110
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#define SICB_ISR0 0xFFC01114
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#define SICB_ISR1 0xFFC01118
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#define SICB_IWR0 0xFFC0111C
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#define SICB_IWR1 0xFFC01120
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#define SICB_IAR0 0xFFC01124
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#define SICB_IAR1 0xFFC01128
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#define SICB_IAR2 0xFFC0112C
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#define SICB_IAR3 0xFFC01130
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#define SICB_IAR4 0xFFC01134
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#define SICB_IAR5 0xFFC01138
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#define SICB_IAR6 0xFFC0113C
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#define SICB_IAR7 0xFFC01140
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#define PPI0_CONTROL 0xFFC01000
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#define PPI0_STATUS 0xFFC01004
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#define PPI0_DELAY 0xFFC0100C
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#define PPI0_COUNT 0xFFC01008
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#define PPI0_FRAME 0xFFC01010
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#define PPI1_CONTROL 0xFFC01300
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#define PPI1_STATUS 0xFFC01304
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#define PPI1_DELAY 0xFFC0130C
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#define PPI1_COUNT 0xFFC01308
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#define PPI1_FRAME 0xFFC01310
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#define TBUFCTL 0xFFE06000
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#define TBUFSTAT 0xFFE06004
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#define TBUF 0xFFE06100
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#define PFCTL 0xFFE08000
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#define PFCNTR0 0xFFE08100
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#define PFCNTR1 0xFFE08104
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#define SRAM_BASE_ADDR_CORE_A 0xFFE00000
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#define SRAM_BASE_ADDR_CORE_B 0xFFE00000
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#define EVT_OVERRIDE 0xFFE02100
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#define UART_THR 0xFFC00400
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#define UART_RBR 0xFFC00400
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#define UART_DLL 0xFFC00400
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#define UART_DLH 0xFFC00404
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#define UART_IER 0xFFC00404
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#define UART_IIR 0xFFC00408
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#define UART_LCR 0xFFC0040C
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#define UART_MCR 0xFFC00410
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#define UART_LSR 0xFFC00414
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#define UART_MSR 0xFFC00418
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#define UART_SCR 0xFFC0041C
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#define UART_GCTL 0xFFC00424
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#define UART_GBL 0xFFC00424
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#define EBIU_AMGCTL 0xFFC00A00
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#define EBIU_AMBCTL0 0xFFC00A04
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#define EBIU_AMBCTL1 0xFFC00A08
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#define EBIU_SDGCTL 0xFFC00A10
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#define EBIU_SDBCTL 0xFFC00A14
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#define EBIU_SDRRC 0xFFC00A18
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#define EBIU_SDSTAT 0xFFC00A1C
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#define L1_INST_SRAM 0xFFA00000 /* 0xFFA00000 -> 0xFFA03FFF Instruction Bank A SRAM */
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#define L1_INST_SRAM_SIZE (0xFFA03FFF - 0xFFA00000 + 1)
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#define L1_INST_SRAM_END (L1_INST_SRAM + L1_INST_SRAM_SIZE)
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#define L1_SRAM_SCRATCH 0xFFB00000 /* 0xFFB00000 -> 0xFFB00FFF Scratchpad SRAM */
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#define L1_SRAM_SCRATCH_SIZE (0xFFB00FFF - 0xFFB00000 + 1)
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#define L1_SRAM_SCRATCH_END (L1_SRAM_SCRATCH + L1_SRAM_SCRATCH_SIZE)
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#define SYSMMR_BASE 0xFFC00000 /* 0xFFC00000 -> 0xFFFFFFFF MMR registers */
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#define SYSMMR_BASE_SIZE (0xFFFFFFFF - 0xFFC00000 + 1)
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#define SYSMMR_BASE_END (SYSMMR_BASE + SYSMMR_BASE_SIZE)
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#endif /* __BFIN_DEF_ADSP_BF561_proc__ */
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