upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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275 lines
6.7 KiB
275 lines
6.7 KiB
/*
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*
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* (C) Copyright 2000-2003
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
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* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/processor.h>
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#include <asm/immap.h>
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DECLARE_GLOBAL_DATA_PTR;
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/* PLL min/max specifications */
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#define MAX_FVCO 500000 /* KHz */
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#define MAX_FSYS 80000 /* KHz */
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#define MIN_FSYS 58333 /* KHz */
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#ifdef CONFIG_MCF5301x
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#define FREF 20000 /* KHz */
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#define MAX_MFD 63 /* Multiplier */
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#define MIN_MFD 0 /* Multiplier */
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#define USBDIV 8
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/* Low Power Divider specifications */
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#define MIN_LPD (0) /* Divider (not encoded) */
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#define MAX_LPD (15) /* Divider (not encoded) */
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#define DEFAULT_LPD (0) /* Divider (not encoded) */
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#endif
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#ifdef CONFIG_MCF532x
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#define FREF 16000 /* KHz */
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#define MAX_MFD 135 /* Multiplier */
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#define MIN_MFD 88 /* Multiplier */
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/* Low Power Divider specifications */
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#define MIN_LPD (1 << 0) /* Divider (not encoded) */
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#define MAX_LPD (1 << 15) /* Divider (not encoded) */
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#define DEFAULT_LPD (1 << 1) /* Divider (not encoded) */
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#endif
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#define BUSDIV 6 /* Divider */
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/* Get the value of the current system clock */
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int get_sys_clock(void)
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{
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volatile ccm_t *ccm = (volatile ccm_t *)(MMAP_CCM);
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volatile pll_t *pll = (volatile pll_t *)(MMAP_PLL);
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int divider;
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/* Test to see if device is in LIMP mode */
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if (ccm->misccr & CCM_MISCCR_LIMP) {
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divider = ccm->cdr & CCM_CDR_LPDIV(0xF);
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#ifdef CONFIG_MCF5301x
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return (FREF / (3 * (1 << divider)));
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#endif
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#ifdef CONFIG_MCF532x
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return (FREF / (2 << divider));
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#endif
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} else {
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#ifdef CONFIG_MCF5301x
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u32 pfdr = (pll->pcr & 0x3F) + 1;
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u32 refdiv = (1 << ((pll->pcr & PLL_PCR_REFDIV(7)) >> 8));
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u32 busdiv = ((pll->pdr & 0x00F0) >> 4) + 1;
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return (((FREF * pfdr) / refdiv) / busdiv);
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#endif
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#ifdef CONFIG_MCF532x
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return ((FREF * pll->pfdr) / (BUSDIV * 4));
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#endif
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}
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}
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/*
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* Initialize the Low Power Divider circuit
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*
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* Parameters:
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* div Desired system frequency divider
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*
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* Return Value:
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* The resulting output system frequency
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*/
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int clock_limp(int div)
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{
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volatile ccm_t *ccm = (volatile ccm_t *)(MMAP_CCM);
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u32 temp;
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/* Check bounds of divider */
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if (div < MIN_LPD)
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div = MIN_LPD;
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if (div > MAX_LPD)
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div = MAX_LPD;
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/* Save of the current value of the SSIDIV so we don't overwrite the value */
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temp = (ccm->cdr & CCM_CDR_SSIDIV(0xFF));
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/* Apply the divider to the system clock */
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ccm->cdr = (CCM_CDR_LPDIV(div) | CCM_CDR_SSIDIV(temp));
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ccm->misccr |= CCM_MISCCR_LIMP;
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return (FREF / (3 * (1 << div)));
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}
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/* Exit low power LIMP mode */
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int clock_exit_limp(void)
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{
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volatile ccm_t *ccm = (volatile ccm_t *)(MMAP_CCM);
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int fout;
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/* Exit LIMP mode */
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ccm->misccr &= (~CCM_MISCCR_LIMP);
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/* Wait for PLL to lock */
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while (!(ccm->misccr & CCM_MISCCR_PLL_LOCK)) ;
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fout = get_sys_clock();
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return fout;
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}
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/* Initialize the PLL
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*
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* Parameters:
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* fref PLL reference clock frequency in KHz
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* fsys Desired PLL output frequency in KHz
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* flags Operating parameters
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*
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* Return Value:
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* The resulting output system frequency
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*/
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int clock_pll(int fsys, int flags)
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{
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#ifdef CONFIG_MCF532x
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volatile u32 *sdram_workaround = (volatile u32 *)(MMAP_SDRAM + 0x80);
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#endif
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volatile sdram_t *sdram = (volatile sdram_t *)(MMAP_SDRAM);
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volatile pll_t *pll = (volatile pll_t *)(MMAP_PLL);
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int fref, temp, fout, mfd;
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u32 i;
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fref = FREF;
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if (fsys == 0) {
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/* Return current PLL output */
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#ifdef CONFIG_MCF5301x
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u32 busdiv = ((pll->pdr >> 4) & 0x0F) + 1;
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mfd = (pll->pcr & 0x3F) + 1;
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return (fref * mfd) / busdiv;
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#endif
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#ifdef CONFIG_MCF532x
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mfd = pll->pfdr;
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return (fref * mfd / (BUSDIV * 4));
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#endif
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}
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/* Check bounds of requested system clock */
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if (fsys > MAX_FSYS)
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fsys = MAX_FSYS;
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if (fsys < MIN_FSYS)
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fsys = MIN_FSYS;
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/*
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* Multiplying by 100 when calculating the temp value,
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* and then dividing by 100 to calculate the mfd allows
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* for exact values without needing to include floating
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* point libraries.
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*/
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temp = (100 * fsys) / fref;
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#ifdef CONFIG_MCF5301x
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mfd = (BUSDIV * temp) / 100;
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/* Determine the output frequency for selected values */
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fout = ((fref * mfd) / BUSDIV);
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#endif
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#ifdef CONFIG_MCF532x
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mfd = (4 * BUSDIV * temp) / 100;
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/* Determine the output frequency for selected values */
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fout = ((fref * mfd) / (BUSDIV * 4));
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#endif
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/* must not tamper with SDRAMC if running from SDRAM */
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#if !defined(CONFIG_MONITOR_IS_IN_RAM)
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/*
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* Check to see if the SDRAM has already been initialized.
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* If it has then the SDRAM needs to be put into self refresh
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* mode before reprogramming the PLL.
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*/
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if (sdram->ctrl & SDRAMC_SDCR_REF)
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sdram->ctrl &= ~SDRAMC_SDCR_CKE;
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/*
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* Initialize the PLL to generate the new system clock frequency.
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* The device must be put into LIMP mode to reprogram the PLL.
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*/
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/* Enter LIMP mode */
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clock_limp(DEFAULT_LPD);
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#ifdef CONFIG_MCF5301x
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pll->pdr =
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PLL_PDR_OUTDIV1((BUSDIV / 3) - 1) |
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PLL_PDR_OUTDIV2(BUSDIV - 1) |
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PLL_PDR_OUTDIV3((BUSDIV / 2) - 1) |
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PLL_PDR_OUTDIV4(USBDIV - 1);
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pll->pcr &= PLL_PCR_FBDIV_UNMASK;
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pll->pcr |= PLL_PCR_FBDIV(mfd - 1);
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#endif
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#ifdef CONFIG_MCF532x
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/* Reprogram PLL for desired fsys */
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pll->podr = (PLL_PODR_CPUDIV(BUSDIV / 3) | PLL_PODR_BUSDIV(BUSDIV));
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pll->pfdr = mfd;
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#endif
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/* Exit LIMP mode */
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clock_exit_limp();
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/* Return the SDRAM to normal operation if it is in use. */
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if (sdram->ctrl & SDRAMC_SDCR_REF)
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sdram->ctrl |= SDRAMC_SDCR_CKE;
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#ifdef CONFIG_MCF532x
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/*
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* software workaround for SDRAM opeartion after exiting LIMP
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* mode errata
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*/
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*sdram_workaround = CONFIG_SYS_SDRAM_BASE;
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#endif
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/* wait for DQS logic to relock */
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for (i = 0; i < 0x200; i++) ;
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#endif /* !defined(CONFIG_MONITOR_IS_IN_RAM) */
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return fout;
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}
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/* get_clocks() fills in gd->cpu_clock and gd->bus_clk */
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int get_clocks(void)
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{
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gd->bus_clk = clock_pll(CONFIG_SYS_CLK / 1000, 0) * 1000;
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gd->cpu_clk = (gd->bus_clk * 3);
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#ifdef CONFIG_FSL_I2C
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gd->i2c1_clk = gd->bus_clk;
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#endif
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return (0);
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}
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