upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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974 lines
24 KiB
974 lines
24 KiB
/*
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* (C) Copyright 2000-2003
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
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* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/immap.h>
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#ifndef CFG_FLASH_CFI
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typedef unsigned char FLASH_PORT_WIDTH;
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typedef volatile unsigned char FLASH_PORT_WIDTHV;
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#define FPW FLASH_PORT_WIDTH
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#define FPWV FLASH_PORT_WIDTHV
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#define CFG_FLASH_CFI_WIDTH FLASH_CFI_8BIT
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#define CFG_FLASH_NONCFI_WIDTH FLASH_CFI_8BIT
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/* Intel-compatible flash commands */
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#define INTEL_PROGRAM 0x00100010
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#define INTEL_ERASE 0x00200020
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#define INTEL_WRSETUP 0x00400040
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#define INTEL_CLEAR 0x00500050
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#define INTEL_LOCKBIT 0x00600060
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#define INTEL_PROTECT 0x00010001
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#define INTEL_STATUS 0x00700070
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#define INTEL_READID 0x00900090
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#define INTEL_CFIQRY 0x00980098
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#define INTEL_SUSERASE 0x00B000B0
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#define INTEL_PROTPROG 0x00C000C0
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#define INTEL_CONFIRM 0x00D000D0
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#define INTEL_WRBLK 0x00e800e8
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#define INTEL_RESET 0x00FF00FF
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/* Intel-compatible flash status bits */
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#define INTEL_FINISHED 0x00800080
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#define INTEL_OK 0x00800080
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#define INTEL_ERASESUS 0x00600060
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#define INTEL_WSM_SUS (INTEL_FINISHED | INTEL_ERASESUS)
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/* 28F160C3B CFI Data offset - This could vary */
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#define INTEL_CFI_MFG 0x00 /* Manufacturer ID */
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#define INTEL_CFI_PART 0x01 /* Product ID */
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#define INTEL_CFI_LOCK 0x02 /* */
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#define INTEL_CFI_TWPRG 0x1F /* Typical Single Word Program Timeout 2^n us */
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#define INTEL_CFI_MBUFW 0x20 /* Typical Max Buffer Write Timeout 2^n us */
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#define INTEL_CFI_TERB 0x21 /* Typical Block Erase Timeout 2^n ms */
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#define INTEL_CFI_MWPRG 0x23 /* Maximum Word program timeout 2^n us */
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#define INTEL_CFI_MERB 0x25 /* Maximum Block Erase Timeout 2^n s */
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#define INTEL_CFI_SIZE 0x27 /* Device size 2^n bytes */
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#define INTEL_CFI_CAP 0x28
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#define INTEL_CFI_WRBUF 0x2A
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#define INTEL_CFI_BANK 0x2C /* Number of Bank */
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#define INTEL_CFI_BLK1A 0x2D /* Number of Blocks */
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#define INTEL_CFI_BLK1B 0x2E /* Number of Blocks */
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#define INTEL_CFI_SZ1A 0x2F /* Block Region Size */
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#define INTEL_CFI_SZ1B 0x30
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#define INTEL_CFI_BLK2A 0x31
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#define INTEL_CFI_BLK2B 0x32
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#define INTEL_CFI_SZ2A 0x33
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#define INTEL_CFI_SZ2B 0x34
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#define FLASH_CYCLE1 0x0555
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#define FLASH_CYCLE2 0x0aaa
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#define WR_BLOCK 0x20
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/* not in the flash.h yet */
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#define FLASH_28F64P30T 0x00B9 /* Intel 28F64P30T ( 64M) */
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#define FLASH_28F64P30B 0x00BA /* Intel 28F64P30B ( 64M) */
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#define FLASH_28F128P30T 0x00BB /* Intel 28F128P30T ( 128M = 8M x 16 ) */
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#define FLASH_28F128P30B 0x00BC /* Intel 28F128P30B ( 128M = 8M x 16 ) */
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#define FLASH_28F256P30T 0x00BD /* Intel 28F256P30T ( 256M = 16M x 16 ) */
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#define FLASH_28F256P30B 0x00BE /* Intel 28F256P30B ( 256M = 16M x 16 ) */
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#define SYNC __asm__("nop")
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/*-----------------------------------------------------------------------
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* Functions
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*/
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ulong flash_get_size(FPWV * addr, flash_info_t * info);
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int flash_get_offsets(ulong base, flash_info_t * info);
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int flash_cmd_rd(volatile u16 * addr, int index);
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int write_data(flash_info_t * info, ulong dest, FPW data);
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int write_data_block(flash_info_t * info, ulong src, ulong dest);
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int write_word_atm(flash_info_t * info, volatile u8 * dest, u16 data);
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void inline spin_wheel(void);
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void flash_sync_real_protect(flash_info_t * info);
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uchar intel_sector_protected(flash_info_t * info, ushort sector);
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flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
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ulong flash_init(void)
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{
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int i;
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ulong size = 0;
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ulong fbase = 0;
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for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
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memset(&flash_info[i], 0, sizeof(flash_info_t));
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switch (i) {
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case 0:
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fbase = (ulong) CFG_FLASH0_BASE;
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break;
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case 1:
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fbase = (ulong) CFG_FLASH1_BASE;
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break;
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}
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flash_get_size((FPWV *) fbase, &flash_info[i]);
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flash_get_offsets((ulong) fbase, &flash_info[i]);
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fbase += flash_info[i].size;
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size += flash_info[i].size;
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/* get the h/w and s/w protection status in sync */
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flash_sync_real_protect(&flash_info[i]);
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}
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/* Protect monitor and environment sectors */
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flash_protect(FLAG_PROTECT_SET,
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CFG_MONITOR_BASE,
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CFG_MONITOR_BASE + monitor_flash_len - 1, &flash_info[0]);
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return size;
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}
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int flash_get_offsets(ulong base, flash_info_t * info)
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{
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int i, j, k;
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int sectors, bs, banks;
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ulong start;
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if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_ATM) {
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int sect[] = CFG_ATMEL_SECT;
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int sectsz[] = CFG_ATMEL_SECTSZ;
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info->start[0] = base;
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for (k = 0, i = 0; i < CFG_ATMEL_REGION; i++) {
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for (j = 0; j < sect[i]; j++, k++) {
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info->start[k + 1] = info->start[k] + sectsz[i];
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info->protect[k] = 0;
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}
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}
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}
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if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
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volatile u16 *addr16 = (volatile u16 *)base;
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*addr16 = (FPW) INTEL_RESET; /* restore read mode */
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*addr16 = (FPW) INTEL_READID;
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banks = addr16[INTEL_CFI_BANK] & 0xff;
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sectors = 0;
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info->start[0] = base;
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for (k = 0, i = 0; i < banks; i++) {
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/* Geometry y1 = y1 + 1, y2 = y2 + 1, CFI spec.
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* To be exact, Z = [0x2f 0x30] (LE) * 256 bytes * [0x2D 0x2E] block count
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* Z = [0x33 0x34] (LE) * 256 bytes * [0x31 0x32] block count
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*/
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bs = ((((addr16[INTEL_CFI_SZ1B + (i * 4)] & 0xff) << 8)
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| (addr16[INTEL_CFI_SZ1A + (i * 4)] & 0xff)) *
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0x100);
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sectors =
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(addr16[INTEL_CFI_BLK1A + (i * 4)] & 0xff) + 1;
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for (j = 0; j < sectors; j++, k++) {
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info->start[k + 1] = info->start[k] + bs;
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}
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}
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*addr16 = (FPW) INTEL_RESET; /* restore read mode */
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}
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return ERR_OK;
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}
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void flash_print_info(flash_info_t * info)
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{
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int i;
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switch (info->flash_id & FLASH_VENDMASK) {
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case FLASH_MAN_INTEL:
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printf("INTEL ");
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break;
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case FLASH_MAN_ATM:
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printf("ATMEL ");
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break;
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default:
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printf("Unknown Vendor ");
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break;
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}
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switch (info->flash_id & FLASH_TYPEMASK) {
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case FLASH_AT040:
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printf("AT49BV040A\n");
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break;
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case FLASH_28F128J3A:
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printf("Intel 28F128J3A\n");
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break;
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default:
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printf("Unknown Chip Type\n");
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return;
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}
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if (info->size > 0x100000) {
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int remainder;
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printf(" Size: %ld", info->size >> 20);
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remainder = (info->size % 0x100000);
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if (remainder) {
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remainder >>= 10;
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remainder = (int)((float)
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(((float)remainder / (float)1024) *
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10000));
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printf(".%d ", remainder);
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}
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printf("MB in %d Sectors\n", info->sector_count);
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} else
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printf(" Size: %ld KB in %d Sectors\n",
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info->size >> 10, info->sector_count);
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printf(" Sector Start Addresses:");
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for (i = 0; i < info->sector_count; ++i) {
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if ((i % 5) == 0)
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printf("\n ");
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printf(" %08lX%s",
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info->start[i], info->protect[i] ? " (RO)" : " ");
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}
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printf("\n");
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}
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/*
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* The following code cannot be run from FLASH!
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*/
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ulong flash_get_size(FPWV * addr, flash_info_t * info)
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{
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volatile u16 *addr16 = (volatile u16 *)addr;
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int intel = 0, banks = 0;
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u16 value;
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int i;
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addr[FLASH_CYCLE1] = (FPWV) 0x00AA00AA; /* for Atmel, Intel ignores this */
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addr[FLASH_CYCLE2] = (FPWV) 0x00550055; /* for Atmel, Intel ignores this */
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addr[FLASH_CYCLE1] = (FPWV) 0x00900090; /* selects Intel or Atmel */
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switch (addr[0] & 0xff) {
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case (u8) ATM_MANUFACT:
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info->flash_id = FLASH_MAN_ATM;
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value = addr[1];
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break;
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case (u8) INTEL_MANUFACT:
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/* Terminate Atmel ID read */
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addr[0] = (FPWV) 0x00F000F0;
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/* Write auto select command: read Manufacturer ID */
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/* Write auto select command sequence and test FLASH answer */
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*addr16 = (FPW) INTEL_RESET; /* restore read mode */
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*addr16 = (FPW) INTEL_READID;
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info->flash_id = FLASH_MAN_INTEL;
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value = (addr16[INTEL_CFI_MFG] << 8);
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value |= addr16[INTEL_CFI_PART] & 0xff;
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intel = 1;
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break;
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default:
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printf("Unknown Flash\n");
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info->flash_id = FLASH_UNKNOWN;
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info->sector_count = 0;
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info->size = 0;
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*addr = (FPW) 0x00F000F0;
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*addr = (FPW) INTEL_RESET; /* restore read mode */
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return (0); /* no or unknown flash */
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}
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switch (value) {
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case (u8) ATM_ID_LV040:
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info->flash_id += FLASH_AT040;
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break;
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case (u16) INTEL_ID_28F128J3:
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info->flash_id += FLASH_28F128J3A;
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break;
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case (u16) INTEL_ID_28F64P30T:
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info->flash_id += FLASH_28F64P30T;
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break;
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case (u16) INTEL_ID_28F64P30B:
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info->flash_id += FLASH_28F64P30B;
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break;
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case (u16) INTEL_ID_28F128P30T:
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info->flash_id += FLASH_28F128P30T;
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break;
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case (u16) INTEL_ID_28F128P30B:
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info->flash_id += FLASH_28F128P30B;
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break;
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case (u16) INTEL_ID_28F256P30T:
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info->flash_id += FLASH_28F256P30T;
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break;
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case (u16) INTEL_ID_28F256P30B:
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info->flash_id += FLASH_28F256P30B;
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break;
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default:
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info->flash_id = FLASH_UNKNOWN;
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break;
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}
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if (intel) {
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/* Intel spec. under CFI section */
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u32 sz;
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int sectors, bs;
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banks = addr16[INTEL_CFI_BANK] & 0xff;
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sectors = sz = 0;
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for (i = 0; i < banks; i++) {
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/* Geometry y1 = y1 + 1, y2 = y2 + 1, CFI spec.
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* To be exact, Z = [0x2f 0x30] (LE) * 256 bytes * [0x2D 0x2E] block count
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* Z = [0x33 0x34] (LE) * 256 bytes * [0x31 0x32] block count
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*/
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bs = ((((addr16[INTEL_CFI_SZ1B + (i * 4)] & 0xff) << 8)
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| (addr16[INTEL_CFI_SZ1A + (i * 4)] & 0xff)) *
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0x100);
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sectors +=
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(addr16[INTEL_CFI_BLK1A + (i * 4)] & 0xff) + 1;
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sz += (bs * sectors);
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}
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info->sector_count = sectors;
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info->size = sz;
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*addr = (FPW) INTEL_RESET; /* restore read mode */
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} else {
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int sect[] = CFG_ATMEL_SECT;
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int sectsz[] = CFG_ATMEL_SECTSZ;
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info->sector_count = 0;
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info->size = 0;
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for (i = 0; i < CFG_ATMEL_REGION; i++) {
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info->sector_count += sect[i];
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info->size += sect[i] * sectsz[i];
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}
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/* reset ID mode */
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addr[0] = (FPWV) 0x00F000F0;
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}
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if (info->sector_count > CFG_MAX_FLASH_SECT) {
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printf("** ERROR: sector count %d > max (%d) **\n",
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info->sector_count, CFG_MAX_FLASH_SECT);
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info->sector_count = CFG_MAX_FLASH_SECT;
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}
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return (info->size);
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}
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|
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int flash_cmd_rd(volatile u16 * addr, int index)
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{
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return (int)addr[index];
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}
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|
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/*
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* This function gets the u-boot flash sector protection status
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* (flash_info_t.protect[]) in sync with the sector protection
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* status stored in hardware.
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*/
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void flash_sync_real_protect(flash_info_t * info)
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{
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int i;
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|
|
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switch (info->flash_id & FLASH_TYPEMASK) {
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case FLASH_28F160C3B:
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case FLASH_28F160C3T:
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case FLASH_28F320C3B:
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case FLASH_28F320C3T:
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case FLASH_28F640C3B:
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case FLASH_28F640C3T:
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for (i = 0; i < info->sector_count; ++i) {
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info->protect[i] = intel_sector_protected(info, i);
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}
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break;
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default:
|
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/* no h/w protect support */
|
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break;
|
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}
|
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}
|
|
|
|
/*
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* checks if "sector" in bank "info" is protected. Should work on intel
|
|
* strata flash chips 28FxxxJ3x in 8-bit mode.
|
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* Returns 1 if sector is protected (or timed-out while trying to read
|
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* protection status), 0 if it is not.
|
|
*/
|
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uchar intel_sector_protected(flash_info_t * info, ushort sector)
|
|
{
|
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FPWV *addr;
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FPWV *lock_conf_addr;
|
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ulong start;
|
|
unsigned char ret;
|
|
|
|
/*
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|
* first, wait for the WSM to be finished. The rationale for
|
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* waiting for the WSM to become idle for at most
|
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* CFG_FLASH_ERASE_TOUT is as follows. The WSM can be busy
|
|
* because of: (1) erase, (2) program or (3) lock bit
|
|
* configuration. So we just wait for the longest timeout of
|
|
* the (1)-(3), i.e. the erase timeout.
|
|
*/
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|
|
/* wait at least 35ns (W12) before issuing Read Status Register */
|
|
/*udelay(1); */
|
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addr = (FPWV *) info->start[sector];
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*addr = (FPW) INTEL_STATUS;
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|
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start = get_timer(0);
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while ((*addr & (FPW) INTEL_FINISHED) != (FPW) INTEL_FINISHED) {
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if (get_timer(start) > CFG_FLASH_UNLOCK_TOUT) {
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*addr = (FPW) INTEL_RESET; /* restore read mode */
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printf("WSM busy too long, can't get prot status\n");
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return 1;
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|
}
|
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}
|
|
|
|
/* issue the Read Identifier Codes command */
|
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*addr = (FPW) INTEL_READID;
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|
|
|
/* Intel example code uses offset of 4 for 8-bit flash */
|
|
lock_conf_addr = (FPWV *) info->start[sector];
|
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ret = (lock_conf_addr[INTEL_CFI_LOCK] & (FPW) INTEL_PROTECT) ? 1 : 0;
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|
|
/* put flash back in read mode */
|
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*addr = (FPW) INTEL_RESET;
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|
|
return ret;
|
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}
|
|
|
|
int flash_erase(flash_info_t * info, int s_first, int s_last)
|
|
{
|
|
int flag, prot, sect;
|
|
ulong type, start, last;
|
|
int rcode = 0, intel = 0;
|
|
|
|
if ((s_first < 0) || (s_first > s_last)) {
|
|
if (info->flash_id == FLASH_UNKNOWN)
|
|
printf("- missing\n");
|
|
else
|
|
printf("- no sectors to erase\n");
|
|
return 1;
|
|
}
|
|
|
|
type = (info->flash_id & FLASH_VENDMASK);
|
|
|
|
if (type != (FLASH_MAN_INTEL & FLASH_VENDMASK)) {
|
|
if (type != (FLASH_MAN_ATM & FLASH_VENDMASK)) {
|
|
type = (info->flash_id & FLASH_VENDMASK);
|
|
printf
|
|
("Can't erase unknown flash type %08lx - aborted\n",
|
|
info->flash_id);
|
|
return 1;
|
|
}
|
|
}
|
|
|
|
if (type == FLASH_MAN_INTEL)
|
|
intel = 1;
|
|
|
|
prot = 0;
|
|
for (sect = s_first; sect <= s_last; ++sect) {
|
|
if (info->protect[sect]) {
|
|
prot++;
|
|
}
|
|
}
|
|
|
|
if (prot)
|
|
printf("- Warning: %d protected sectors will not be erased!\n",
|
|
prot);
|
|
else
|
|
printf("\n");
|
|
|
|
start = get_timer(0);
|
|
last = start;
|
|
|
|
/* Start erase on unprotected sectors */
|
|
for (sect = s_first; sect <= s_last; sect++) {
|
|
if (info->protect[sect] == 0) { /* not protected */
|
|
|
|
FPWV *addr = (FPWV *) (info->start[sect]);
|
|
int min = 0;
|
|
|
|
printf(".");
|
|
|
|
/* arm simple, non interrupt dependent timer */
|
|
start = get_timer(0);
|
|
|
|
if (intel) {
|
|
*addr = (FPW) INTEL_READID;
|
|
min = addr[INTEL_CFI_TERB] & 0xff;
|
|
min = 1 << min; /* ms */
|
|
min = (min / info->sector_count) * 1000;
|
|
|
|
/* start erase block */
|
|
*addr = (FPW) INTEL_CLEAR; /* clear status register */
|
|
*addr = (FPW) INTEL_ERASE; /* erase setup */
|
|
*addr = (FPW) INTEL_CONFIRM; /* erase confirm */
|
|
|
|
while ((*addr & (FPW) INTEL_FINISHED) !=
|
|
(FPW) INTEL_FINISHED) {
|
|
|
|
if (get_timer(start) >
|
|
CFG_FLASH_ERASE_TOUT) {
|
|
printf("Timeout\n");
|
|
*addr = (FPW) INTEL_SUSERASE; /* suspend erase */
|
|
*addr = (FPW) INTEL_RESET; /* reset to read mode */
|
|
|
|
rcode = 1;
|
|
break;
|
|
}
|
|
}
|
|
|
|
*addr = (FPW) INTEL_RESET; /* resest to read mode */
|
|
} else {
|
|
FPWV *base; /* first address in bank */
|
|
FPWV *atmeladdr;
|
|
|
|
flag = disable_interrupts();
|
|
|
|
atmeladdr = (FPWV *) addr; /* concatenate to 8 bit */
|
|
base = (FPWV *) (CFG_ATMEL_BASE); /* First sector */
|
|
|
|
base[FLASH_CYCLE1] = (u8) 0x00AA00AA; /* unlock */
|
|
base[FLASH_CYCLE2] = (u8) 0x00550055; /* unlock */
|
|
base[FLASH_CYCLE1] = (u8) 0x00800080; /* erase mode */
|
|
base[FLASH_CYCLE1] = (u8) 0x00AA00AA; /* unlock */
|
|
base[FLASH_CYCLE2] = (u8) 0x00550055; /* unlock */
|
|
*atmeladdr = (u8) 0x00300030; /* erase sector */
|
|
|
|
if (flag)
|
|
enable_interrupts();
|
|
|
|
while ((*atmeladdr & (u8) 0x00800080) !=
|
|
(u8) 0x00800080) {
|
|
if (get_timer(start) >
|
|
CFG_FLASH_ERASE_TOUT) {
|
|
printf("Timeout\n");
|
|
*atmeladdr = (u8) 0x00F000F0; /* reset to read mode */
|
|
|
|
rcode = 1;
|
|
break;
|
|
}
|
|
}
|
|
|
|
*atmeladdr = (u8) 0x00F000F0; /* reset to read mode */
|
|
} /* Atmel or Intel */
|
|
}
|
|
}
|
|
printf(" done\n");
|
|
|
|
return rcode;
|
|
}
|
|
|
|
int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt)
|
|
{
|
|
if (info->flash_id == FLASH_UNKNOWN)
|
|
return 4;
|
|
|
|
switch (info->flash_id & FLASH_VENDMASK) {
|
|
case FLASH_MAN_ATM:
|
|
{
|
|
u16 data = 0;
|
|
int bytes; /* number of bytes to program in current word */
|
|
int left; /* number of bytes left to program */
|
|
int i, res;
|
|
|
|
for (left = cnt, res = 0;
|
|
left > 0 && res == 0;
|
|
addr += sizeof(data), left -=
|
|
sizeof(data) - bytes) {
|
|
|
|
bytes = addr & (sizeof(data) - 1);
|
|
addr &= ~(sizeof(data) - 1);
|
|
|
|
/* combine source and destination data so can program
|
|
* an entire word of 16 or 32 bits
|
|
*/
|
|
for (i = 0; i < sizeof(data); i++) {
|
|
data <<= 8;
|
|
if (i < bytes || i - bytes >= left)
|
|
data += *((uchar *) addr + i);
|
|
else
|
|
data += *src++;
|
|
}
|
|
|
|
data = (data >> 8) | (data << 8);
|
|
res = write_word_atm(info, (FPWV *) addr, data);
|
|
}
|
|
return res;
|
|
} /* case FLASH_MAN_ATM */
|
|
|
|
case FLASH_MAN_INTEL:
|
|
{
|
|
ulong cp, wp;
|
|
u16 data;
|
|
int count, i, l, rc, port_width;
|
|
|
|
/* get lower word aligned address */
|
|
wp = addr;
|
|
port_width = sizeof(FPW);
|
|
|
|
/*
|
|
* handle unaligned start bytes
|
|
*/
|
|
if ((l = addr - wp) != 0) {
|
|
data = 0;
|
|
for (i = 0, cp = wp; i < l; ++i, ++cp) {
|
|
data = (data << 8) | (*(uchar *) cp);
|
|
}
|
|
|
|
for (; i < port_width && cnt > 0; ++i) {
|
|
data = (data << 8) | *src++;
|
|
--cnt;
|
|
++cp;
|
|
}
|
|
|
|
for (; cnt == 0 && i < port_width; ++i, ++cp)
|
|
data = (data << 8) | (*(uchar *) cp);
|
|
|
|
if ((rc = write_data(info, wp, data)) != 0)
|
|
return (rc);
|
|
|
|
wp += port_width;
|
|
}
|
|
|
|
if (cnt > WR_BLOCK) {
|
|
/*
|
|
* handle word aligned part
|
|
*/
|
|
count = 0;
|
|
while (cnt >= WR_BLOCK) {
|
|
|
|
if ((rc =
|
|
write_data_block(info,
|
|
(ulong) src,
|
|
wp)) != 0)
|
|
return (rc);
|
|
|
|
wp += WR_BLOCK;
|
|
src += WR_BLOCK;
|
|
cnt -= WR_BLOCK;
|
|
|
|
if (count++ > 0x800) {
|
|
spin_wheel();
|
|
count = 0;
|
|
}
|
|
}
|
|
}
|
|
|
|
/* handle word aligned part */
|
|
if (cnt < WR_BLOCK) {
|
|
/*
|
|
* handle word aligned part
|
|
*/
|
|
count = 0;
|
|
while (cnt >= port_width) {
|
|
data = 0;
|
|
for (i = 0; i < port_width; ++i)
|
|
data = (data << 8) | *src++;
|
|
|
|
if ((rc =
|
|
write_data(info,
|
|
(ulong) ((FPWV *) wp),
|
|
(FPW) (data))) != 0)
|
|
return (rc);
|
|
|
|
wp += port_width;
|
|
cnt -= port_width;
|
|
if (count++ > 0x800) {
|
|
spin_wheel();
|
|
count = 0;
|
|
}
|
|
}
|
|
}
|
|
|
|
if (cnt == 0)
|
|
return ERR_OK;
|
|
|
|
/*
|
|
* handle unaligned tail bytes
|
|
*/
|
|
data = 0;
|
|
for (i = 0, cp = wp; i < port_width && cnt > 0;
|
|
++i, ++cp) {
|
|
data = (data << 8) | (*src++);
|
|
--cnt;
|
|
}
|
|
for (; i < port_width; ++i, ++cp) {
|
|
data = (data << 8) | (*(uchar *) cp);
|
|
}
|
|
|
|
return write_data(info, (ulong) ((FPWV *) wp),
|
|
(FPW) data);
|
|
|
|
} /* case FLASH_MAN_INTEL */
|
|
|
|
} /* switch */
|
|
|
|
return ERR_OK;
|
|
}
|
|
|
|
/*-----------------------------------------------------------------------
|
|
* Write a word or halfword to Flash, returns:
|
|
* 0 - OK
|
|
* 1 - write timeout
|
|
* 2 - Flash not erased
|
|
*/
|
|
int write_data_block(flash_info_t * info, ulong src, ulong dest)
|
|
{
|
|
FPWV *srcaddr = (FPWV *) src;
|
|
FPWV *dstaddr = (FPWV *) dest;
|
|
ulong start;
|
|
int flag, i;
|
|
|
|
/* Check if Flash is (sufficiently) erased */
|
|
for (i = 0; i < WR_BLOCK; i++)
|
|
if ((*dstaddr++ & 0xff) != 0xff) {
|
|
printf("not erased at %08lx (%lx)\n",
|
|
(ulong) dstaddr, *dstaddr);
|
|
return (2);
|
|
}
|
|
|
|
dstaddr = (FPWV *) dest;
|
|
|
|
/* Disable interrupts which might cause a timeout here */
|
|
flag = disable_interrupts();
|
|
|
|
*dstaddr = (FPW) INTEL_WRBLK; /* write block setup */
|
|
|
|
if (flag)
|
|
enable_interrupts();
|
|
|
|
/* arm simple, non interrupt dependent timer */
|
|
start = get_timer(0);
|
|
|
|
/* wait while polling the status register */
|
|
while ((*dstaddr & (FPW) INTEL_FINISHED) != (FPW) INTEL_OK) {
|
|
if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
|
|
*dstaddr = (FPW) INTEL_RESET; /* restore read mode */
|
|
return (1);
|
|
}
|
|
}
|
|
|
|
*dstaddr = (FPW) WR_BLOCK - 1; /* write 32 to buffer */
|
|
for (i = 0; i < WR_BLOCK; i++)
|
|
*dstaddr++ = *srcaddr++;
|
|
|
|
dstaddr -= 1;
|
|
*dstaddr = (FPW) INTEL_CONFIRM; /* write 32 to buffer */
|
|
|
|
/* arm simple, non interrupt dependent timer */
|
|
start = get_timer(0);
|
|
|
|
/* wait while polling the status register */
|
|
while ((*dstaddr & (FPW) INTEL_FINISHED) != (FPW) INTEL_OK) {
|
|
if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
|
|
*dstaddr = (FPW) INTEL_RESET; /* restore read mode */
|
|
return (1);
|
|
}
|
|
}
|
|
|
|
*dstaddr = (FPW) INTEL_RESET; /* restore read mode */
|
|
|
|
return (0);
|
|
}
|
|
|
|
/*-----------------------------------------------------------------------
|
|
* Write a word or halfword to Flash, returns:
|
|
* 0 - OK
|
|
* 1 - write timeout
|
|
* 2 - Flash not erased
|
|
*/
|
|
int write_data(flash_info_t * info, ulong dest, FPW data)
|
|
{
|
|
FPWV *addr = (FPWV *) dest;
|
|
ulong start;
|
|
int flag;
|
|
|
|
/* Check if Flash is (sufficiently) erased */
|
|
if ((*addr & data) != data) {
|
|
printf("not erased at %08lx (%lx)\n", (ulong) addr,
|
|
(ulong) * addr);
|
|
return (2);
|
|
}
|
|
|
|
/* Disable interrupts which might cause a timeout here */
|
|
flag = (int)disable_interrupts();
|
|
|
|
*addr = (FPW) INTEL_CLEAR;
|
|
*addr = (FPW) INTEL_RESET;
|
|
|
|
*addr = (FPW) INTEL_WRSETUP; /* write setup */
|
|
*addr = data;
|
|
|
|
if (flag)
|
|
enable_interrupts();
|
|
|
|
/* arm simple, non interrupt dependent timer */
|
|
start = get_timer(0);
|
|
|
|
/* wait while polling the status register */
|
|
while ((*addr & (FPW) INTEL_OK) != (FPW) INTEL_OK) {
|
|
if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
|
|
*addr = (FPW) INTEL_SUSERASE; /* suspend mode */
|
|
*addr = (FPW) INTEL_CLEAR; /* clear status */
|
|
*addr = (FPW) INTEL_RESET; /* reset */
|
|
return (1);
|
|
}
|
|
}
|
|
|
|
*addr = (FPW) INTEL_CLEAR; /* clear status */
|
|
*addr = (FPW) INTEL_RESET; /* restore read mode */
|
|
|
|
return (0);
|
|
}
|
|
|
|
/*-----------------------------------------------------------------------
|
|
* Write a word to Flash for ATMEL FLASH
|
|
* A word is 16 bits, whichever the bus width of the flash bank
|
|
* (not an individual chip) is.
|
|
*
|
|
* returns:
|
|
* 0 - OK
|
|
* 1 - write timeout
|
|
* 2 - Flash not erased
|
|
*/
|
|
int write_word_atm(flash_info_t * info, volatile u8 * dest, u16 data)
|
|
{
|
|
ulong start;
|
|
int flag, i;
|
|
int res = 0; /* result, assume success */
|
|
FPWV *base; /* first address in flash bank */
|
|
|
|
/* Check if Flash is (sufficiently) erased */
|
|
if ((*((volatile u16 *)dest) & data) != data) {
|
|
return (2);
|
|
}
|
|
|
|
base = (FPWV *) (CFG_ATMEL_BASE);
|
|
|
|
for (i = 0; i < sizeof(u16); i++) {
|
|
/* Disable interrupts which might cause a timeout here */
|
|
flag = disable_interrupts();
|
|
|
|
base[FLASH_CYCLE1] = (u8) 0x00AA00AA; /* unlock */
|
|
base[FLASH_CYCLE2] = (u8) 0x00550055; /* unlock */
|
|
base[FLASH_CYCLE1] = (u8) 0x00A000A0; /* selects program mode */
|
|
|
|
*dest = data; /* start programming the data */
|
|
|
|
/* re-enable interrupts if necessary */
|
|
if (flag)
|
|
enable_interrupts();
|
|
|
|
start = get_timer(0);
|
|
|
|
/* data polling for D7 */
|
|
while (res == 0
|
|
&& (*dest & (u8) 0x00800080) !=
|
|
(data & (u8) 0x00800080)) {
|
|
if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
|
|
*dest = (u8) 0x00F000F0; /* reset bank */
|
|
res = 1;
|
|
}
|
|
}
|
|
|
|
*dest++ = (u8) 0x00F000F0; /* reset bank */
|
|
data >>= 8;
|
|
}
|
|
|
|
return (res);
|
|
}
|
|
|
|
void inline spin_wheel(void)
|
|
{
|
|
static int p = 0;
|
|
static char w[] = "\\/-";
|
|
|
|
printf("\010%c", w[p]);
|
|
(++p == 3) ? (p = 0) : 0;
|
|
}
|
|
|
|
#ifdef CFG_FLASH_PROTECTION
|
|
/*-----------------------------------------------------------------------
|
|
*/
|
|
int flash_real_protect(flash_info_t * info, long sector, int prot)
|
|
{
|
|
int rcode = 0; /* assume success */
|
|
FPWV *addr; /* address of sector */
|
|
FPW value;
|
|
|
|
addr = (FPWV *) (info->start[sector]);
|
|
|
|
switch (info->flash_id & FLASH_TYPEMASK) {
|
|
case FLASH_28F160C3B:
|
|
case FLASH_28F160C3T:
|
|
case FLASH_28F320C3B:
|
|
case FLASH_28F320C3T:
|
|
case FLASH_28F640C3B:
|
|
case FLASH_28F640C3T:
|
|
*addr = (FPW) INTEL_RESET; /* make sure in read mode */
|
|
*addr = (FPW) INTEL_LOCKBIT; /* lock command setup */
|
|
|
|
if (prot)
|
|
*addr = (FPW) INTEL_PROTECT; /* lock sector */
|
|
else
|
|
*addr = (FPW) INTEL_CONFIRM; /* unlock sector */
|
|
|
|
/* now see if it really is locked/unlocked as requested */
|
|
*addr = (FPW) INTEL_READID;
|
|
|
|
/* read sector protection at sector address, (A7 .. A0) = 0x02.
|
|
* D0 = 1 for each device if protected.
|
|
* If at least one device is protected the sector is marked
|
|
* protected, but return failure. Mixed protected and
|
|
* unprotected devices within a sector should never happen.
|
|
*/
|
|
value = addr[2] & (FPW) INTEL_PROTECT;
|
|
if (value == 0)
|
|
info->protect[sector] = 0;
|
|
else if (value == (FPW) INTEL_PROTECT)
|
|
info->protect[sector] = 1;
|
|
else {
|
|
/* error, mixed protected and unprotected */
|
|
rcode = 1;
|
|
info->protect[sector] = 1;
|
|
}
|
|
if (info->protect[sector] != prot)
|
|
rcode = 1; /* failed to protect/unprotect as requested */
|
|
|
|
/* reload all protection bits from hardware for now */
|
|
flash_sync_real_protect(info);
|
|
break;
|
|
|
|
default:
|
|
/* no hardware protect that we support */
|
|
info->protect[sector] = prot;
|
|
break;
|
|
}
|
|
|
|
return rcode;
|
|
}
|
|
#endif
|
|
#endif
|
|
|