upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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130 lines
3.7 KiB
130 lines
3.7 KiB
/*
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* (C) Copyright 2000-2003
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <mpc8220.h>
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/*
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* Breath some life into the CPU...
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*
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* Set up the memory map,
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* initialize a bunch of registers.
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*/
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void cpu_init_f (void)
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{
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DECLARE_GLOBAL_DATA_PTR;
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volatile flexbus8220_t *flexbus = (volatile flexbus8220_t *) MMAP_FB;
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volatile pcfg8220_t *portcfg = (volatile pcfg8220_t *) MMAP_PCFG;
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volatile xlbarb8220_t *xlbarb = (volatile xlbarb8220_t *) MMAP_XLBARB;
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/* Pointer is writable since we allocated a register for it */
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gd = (gd_t *) (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET);
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/* Clear initial global data */
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memset ((void *) gd, 0, sizeof (gd_t));
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/* Clear all port configuration */
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portcfg->pcfg0 = 0;
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portcfg->pcfg1 = 0;
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portcfg->pcfg2 = 0;
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portcfg->pcfg3 = 0;
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/*
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* Flexbus Controller: configure chip selects and enable them
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*/
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#if defined (CFG_CS0_BASE)
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flexbus->csar0 = CFG_CS0_BASE;
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flexbus->cscr0 = CFG_CS0_CTRL;
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flexbus->csmr0 = ((CFG_CS0_MASK - 1) & 0xffff0000) | 1;
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__asm__ volatile ("sync");
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#endif
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#if defined (CFG_CS1_BASE)
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flexbus->csar1 = CFG_CS1_BASE;
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flexbus->cscr1 = CFG_CS1_CTRL;
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flexbus->csmr1 = ((CFG_CS1_MASK - 1) & 0xffff0000) | 1;
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__asm__ volatile ("sync");
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#endif
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#if defined (CFG_CS2_BASE)
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flexbus->csar2 = CFG_CS2_BASE;
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flexbus->cscr2 = CFG_CS2_CTRL;
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flexbus->csmr2 = ((CFG_CS2_MASK - 1) & 0xffff0000) | 1;
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portcfg->pcfg3 |= CFG_CS2_PORT3_CONFIG;
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__asm__ volatile ("sync");
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#endif
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#if defined (CFG_CS3_BASE)
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flexbus->csar3 = CFG_CS3_BASE;
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flexbus->cscr3 = CFG_CS3_CTRL;
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flexbus->csmr3 = ((CFG_CS3_MASK - 1) & 0xffff0000) | 1;
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portcfg->pcfg3 |= CFG_CS3_PORT3_CONFIG;
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__asm__ volatile ("sync");
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#endif
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#if defined (CFG_CS4_BASE)
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flexbus->csar4 = CFG_CS4_BASE;
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flexbus->cscr4 = CFG_CS4_CTRL;
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flexbus->csmr4 = ((CFG_CS4_MASK - 1) & 0xffff0000) | 1;
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portcfg->pcfg3 |= CFG_CS4_PORT3_CONFIG;
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__asm__ volatile ("sync");
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#endif
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#if defined (CFG_CS5_BASE)
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flexbus->csar5 = CFG_CS5_BASE;
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flexbus->cscr5 = CFG_CS5_CTRL;
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flexbus->csmr5 = ((CFG_CS5_MASK - 1) & 0xffff0000) | 1;
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portcfg->pcfg3 |= CFG_CS5_PORT3_CONFIG;
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__asm__ volatile ("sync");
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#endif
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/* This section of the code cannot place in cpu_init_r(),
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it will cause the system to hang */
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/* enable timebase */
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xlbarb->config = 0x00002000;
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xlbarb->addrTenTimeOut = 0x1000;
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xlbarb->dataTenTimeOut = 0x1000;
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xlbarb->busActTimeOut = 0x2000;
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/* Master Priority Enable */
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xlbarb->mastPriEn = 0x1f;
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xlbarb->mastPriority = 0;
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}
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/*
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* initialize higher level parts of CPU like time base and timers
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*/
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int cpu_init_r (void)
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{
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/* this may belongs to disable interrupt section */
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/* mask all interrupts */
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*(vu_long *) 0xf0000700 = 0xfffffc00;
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*(vu_long *) 0xf0000714 |= 0x0001ffff;
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*(vu_long *) 0xf0000710 &= ~0x00000f00;
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/* route critical ints to normal ints */
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*(vu_long *) 0xf0000710 |= 0x00000001;
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#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_MPC8220_FEC)
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/* load FEC microcode */
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loadtask (0, 2);
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#endif
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return (0);
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}
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