upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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62 lines
1.2 KiB
62 lines
1.2 KiB
/*
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* (C) Copyright 2000-2004
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <mpc8xx.h>
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#include <asm/processor.h>
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DECLARE_GLOBAL_DATA_PTR;
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void get_brgclk(uint sccr)
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{
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uint divider = 0;
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switch((sccr&SCCR_DFBRG11)>>11){
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case 0:
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divider = 1;
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break;
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case 1:
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divider = 4;
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break;
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case 2:
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divider = 16;
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break;
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case 3:
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divider = 64;
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break;
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}
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gd->arch.brg_clk = gd->cpu_clk/divider;
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}
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/*
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* get_clocks() fills in gd->cpu_clock depending on CONFIG_8xx_GCLK_FREQ
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*/
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int get_clocks (void)
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{
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uint immr = get_immr (0); /* Return full IMMR contents */
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volatile immap_t *immap = (immap_t *) (immr & 0xFFFF0000);
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uint sccr = immap->im_clkrst.car_sccr;
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/*
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* If for some reason measuring the gclk frequency won't
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* work, we return the hardwired value.
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* (For example, the cogent CMA286-60 CPU module has no
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* separate oscillator for PITRTCLK)
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*/
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gd->cpu_clk = CONFIG_8xx_GCLK_FREQ;
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if ((sccr & SCCR_EBDF11) == 0) {
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/* No Bus Divider active */
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gd->bus_clk = gd->cpu_clk;
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} else {
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/* The MPC8xx has only one BDF: half clock speed */
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gd->bus_clk = gd->cpu_clk / 2;
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}
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get_brgclk(sccr);
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return (0);
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}
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