upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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301 lines
6.2 KiB
301 lines
6.2 KiB
/*
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* K2HK EVM : Board initialization
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*
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* (C) Copyright 2012-2014
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* Texas Instruments Incorporated, <www.ti.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <exports.h>
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#include <fdt_support.h>
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#include <libfdt.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/clock.h>
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#include <asm/io.h>
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#include <asm/mach-types.h>
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#include <asm/arch/emac_defs.h>
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#include <asm/arch/psc_defs.h>
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#include <asm/ti-common/ti-aemif.h>
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DECLARE_GLOBAL_DATA_PTR;
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u32 device_big_endian;
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unsigned int external_clk[ext_clk_count] = {
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[sys_clk] = 122880000,
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[alt_core_clk] = 125000000,
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[pa_clk] = 122880000,
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[tetris_clk] = 125000000,
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[ddr3a_clk] = 100000000,
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[ddr3b_clk] = 100000000,
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[mcm_clk] = 312500000,
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[pcie_clk] = 100000000,
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[sgmii_srio_clk] = 156250000,
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[xgmii_clk] = 156250000,
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[usb_clk] = 100000000,
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[rp1_clk] = 123456789 /* TODO: cannot find
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what is that */
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};
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static struct aemif_config aemif_configs[] = {
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{ /* CS0 */
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.mode = AEMIF_MODE_NAND,
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.wr_setup = 0xf,
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.wr_strobe = 0x3f,
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.wr_hold = 7,
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.rd_setup = 0xf,
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.rd_strobe = 0x3f,
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.rd_hold = 7,
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.turn_around = 3,
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.width = AEMIF_WIDTH_8,
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},
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};
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static struct pll_init_data pll_config[] = {
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CORE_PLL_1228,
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PASS_PLL_983,
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TETRIS_PLL_1200,
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};
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int dram_init(void)
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{
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init_ddr3();
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gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
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CONFIG_MAX_RAM_BANK_SIZE);
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aemif_init(ARRAY_SIZE(aemif_configs), aemif_configs);
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return 0;
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}
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#ifdef CONFIG_DRIVER_TI_KEYSTONE_NET
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struct eth_priv_t eth_priv_cfg[] = {
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{
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.int_name = "K2HK_EMAC",
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.rx_flow = 22,
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.phy_addr = 0,
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.slave_port = 1,
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.sgmii_link_type = SGMII_LINK_MAC_PHY,
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},
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{
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.int_name = "K2HK_EMAC1",
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.rx_flow = 23,
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.phy_addr = 1,
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.slave_port = 2,
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.sgmii_link_type = SGMII_LINK_MAC_PHY,
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},
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{
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.int_name = "K2HK_EMAC2",
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.rx_flow = 24,
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.phy_addr = 2,
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.slave_port = 3,
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.sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED,
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},
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{
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.int_name = "K2HK_EMAC3",
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.rx_flow = 25,
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.phy_addr = 3,
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.slave_port = 4,
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.sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED,
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},
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};
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int get_eth_env_param(char *env_name)
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{
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char *env;
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int res = -1;
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env = getenv(env_name);
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if (env)
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res = simple_strtol(env, NULL, 0);
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return res;
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}
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int board_eth_init(bd_t *bis)
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{
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int j;
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int res;
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char link_type_name[32];
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for (j = 0; j < (sizeof(eth_priv_cfg) / sizeof(struct eth_priv_t));
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j++) {
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sprintf(link_type_name, "sgmii%d_link_type", j);
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res = get_eth_env_param(link_type_name);
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if (res >= 0)
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eth_priv_cfg[j].sgmii_link_type = res;
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keystone2_emac_initialize(ð_priv_cfg[j]);
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}
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return 0;
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}
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#endif
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/* Byte swap the 32-bit data if the device is BE */
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int cpu_to_bus(u32 *ptr, u32 length)
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{
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u32 i;
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if (device_big_endian)
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for (i = 0; i < length; i++, ptr++)
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*ptr = __swab32(*ptr);
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return 0;
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}
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#if defined(CONFIG_BOARD_EARLY_INIT_F)
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int board_early_init_f(void)
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{
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init_plls(ARRAY_SIZE(pll_config), pll_config);
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return 0;
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}
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#endif
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int board_init(void)
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{
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gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
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return 0;
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}
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#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
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#define K2_DDR3_START_ADDR 0x80000000
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void ft_board_setup(void *blob, bd_t *bd)
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{
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u64 start[2];
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u64 size[2];
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char name[32], *env, *endp;
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int lpae, nodeoffset;
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u32 ddr3a_size;
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int nbanks;
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env = getenv("mem_lpae");
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lpae = env && simple_strtol(env, NULL, 0);
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ddr3a_size = 0;
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if (lpae) {
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env = getenv("ddr3a_size");
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if (env)
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ddr3a_size = simple_strtol(env, NULL, 10);
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if ((ddr3a_size != 8) && (ddr3a_size != 4))
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ddr3a_size = 0;
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}
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nbanks = 1;
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start[0] = bd->bi_dram[0].start;
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size[0] = bd->bi_dram[0].size;
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/* adjust memory start address for LPAE */
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if (lpae) {
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start[0] -= K2_DDR3_START_ADDR;
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start[0] += CONFIG_SYS_LPAE_SDRAM_BASE;
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}
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if ((size[0] == 0x80000000) && (ddr3a_size != 0)) {
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size[1] = ((u64)ddr3a_size - 2) << 30;
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start[1] = 0x880000000;
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nbanks++;
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}
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/* reserve memory at start of bank */
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sprintf(name, "mem_reserve_head");
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env = getenv(name);
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if (env) {
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start[0] += ustrtoul(env, &endp, 0);
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size[0] -= ustrtoul(env, &endp, 0);
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}
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sprintf(name, "mem_reserve");
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env = getenv(name);
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if (env)
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size[0] -= ustrtoul(env, &endp, 0);
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fdt_fixup_memory_banks(blob, start, size, nbanks);
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/* Fix up the initrd */
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if (lpae) {
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u64 initrd_start, initrd_end;
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u32 *prop1, *prop2;
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int err;
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nodeoffset = fdt_path_offset(blob, "/chosen");
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if (nodeoffset >= 0) {
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prop1 = (u32 *)fdt_getprop(blob, nodeoffset,
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"linux,initrd-start", NULL);
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prop2 = (u32 *)fdt_getprop(blob, nodeoffset,
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"linux,initrd-end", NULL);
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if (prop1 && prop2) {
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initrd_start = __be32_to_cpu(*prop1);
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initrd_start -= K2_DDR3_START_ADDR;
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initrd_start += CONFIG_SYS_LPAE_SDRAM_BASE;
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initrd_start = __cpu_to_be64(initrd_start);
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initrd_end = __be32_to_cpu(*prop2);
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initrd_end -= K2_DDR3_START_ADDR;
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initrd_end += CONFIG_SYS_LPAE_SDRAM_BASE;
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initrd_end = __cpu_to_be64(initrd_end);
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err = fdt_delprop(blob, nodeoffset,
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"linux,initrd-start");
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if (err < 0)
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puts("error deleting initrd-start\n");
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err = fdt_delprop(blob, nodeoffset,
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"linux,initrd-end");
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if (err < 0)
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puts("error deleting initrd-end\n");
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err = fdt_setprop(blob, nodeoffset,
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"linux,initrd-start",
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&initrd_start,
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sizeof(initrd_start));
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if (err < 0)
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puts("error adding initrd-start\n");
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err = fdt_setprop(blob, nodeoffset,
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"linux,initrd-end",
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&initrd_end,
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sizeof(initrd_end));
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if (err < 0)
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puts("error adding linux,initrd-end\n");
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}
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}
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}
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}
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void ft_board_setup_ex(void *blob, bd_t *bd)
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{
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int lpae;
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char *env;
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u64 *reserve_start, size;
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env = getenv("mem_lpae");
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lpae = env && simple_strtol(env, NULL, 0);
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if (lpae) {
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/*
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* the initrd and other reserved memory areas are
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* embedded in in the DTB itslef. fix up these addresses
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* to 36 bit format
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*/
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reserve_start = (u64 *)((char *)blob +
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fdt_off_mem_rsvmap(blob));
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while (1) {
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*reserve_start = __cpu_to_be64(*reserve_start);
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size = __cpu_to_be64(*(reserve_start + 1));
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if (size) {
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*reserve_start -= K2_DDR3_START_ADDR;
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*reserve_start +=
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CONFIG_SYS_LPAE_SDRAM_BASE;
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*reserve_start =
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__cpu_to_be64(*reserve_start);
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} else {
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break;
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}
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reserve_start += 2;
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}
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}
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}
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#endif
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