upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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72 lines
1.5 KiB
72 lines
1.5 KiB
/*
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* Copyright (C) 2015 Freescale Semiconductor
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __LDPAA_WRIOP_H
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#define __LDPAA_WRIOP_H
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#include <phy.h>
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enum wriop_port {
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WRIOP1_DPMAC1 = 1,
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WRIOP1_DPMAC2,
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WRIOP1_DPMAC3,
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WRIOP1_DPMAC4,
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WRIOP1_DPMAC5,
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WRIOP1_DPMAC6,
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WRIOP1_DPMAC7,
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WRIOP1_DPMAC8,
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WRIOP1_DPMAC9,
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WRIOP1_DPMAC10,
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WRIOP1_DPMAC11,
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WRIOP1_DPMAC12,
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WRIOP1_DPMAC13,
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WRIOP1_DPMAC14,
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WRIOP1_DPMAC15,
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WRIOP1_DPMAC16,
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WRIOP1_DPMAC17,
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WRIOP1_DPMAC18,
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WRIOP1_DPMAC19,
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WRIOP1_DPMAC20,
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WRIOP1_DPMAC21,
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WRIOP1_DPMAC22,
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WRIOP1_DPMAC23,
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WRIOP1_DPMAC24,
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NUM_WRIOP_PORTS,
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};
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struct wriop_dpmac_info {
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u8 enabled;
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u8 id;
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u8 board_mux;
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int phy_addr;
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void *phy_regs;
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phy_interface_t enet_if;
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struct phy_device *phydev;
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struct mii_dev *bus;
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};
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extern struct wriop_dpmac_info dpmac_info[NUM_WRIOP_PORTS];
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#define DEFAULT_WRIOP_MDIO1_NAME "FSL_MDIO0"
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#define DEFAULT_WRIOP_MDIO2_NAME "FSL_MDIO1"
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void wriop_init_dpmac(int, int, int);
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void wriop_disable_dpmac(int);
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void wriop_enable_dpmac(int);
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u8 wriop_is_enabled_dpmac(int dpmac_id);
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void wriop_set_mdio(int, struct mii_dev *);
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struct mii_dev *wriop_get_mdio(int);
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void wriop_set_phy_address(int, int);
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int wriop_get_phy_address(int);
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void wriop_set_phy_dev(int, struct phy_device *);
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struct phy_device *wriop_get_phy_dev(int);
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phy_interface_t wriop_get_enet_if(int);
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void wriop_dpmac_disable(int);
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void wriop_dpmac_enable(int);
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phy_interface_t wriop_dpmac_enet_if(int, int);
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void wriop_init_dpmac_qsgmii(int, int);
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#endif /* __LDPAA_WRIOP_H */
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