upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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95 lines
1.8 KiB
95 lines
1.8 KiB
/*
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* K2G EVM : Board initialization
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*
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* (C) Copyright 2015
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* Texas Instruments Incorporated, <www.ti.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/arch/clock.h>
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#include <asm/ti-common/keystone_net.h>
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#include "mux-k2g.h"
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#define SYS_CLK 24000000
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unsigned int external_clk[ext_clk_count] = {
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[sys_clk] = SYS_CLK,
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[pa_clk] = SYS_CLK,
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[tetris_clk] = SYS_CLK,
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[ddr3a_clk] = SYS_CLK,
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[uart_clk] = SYS_CLK,
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};
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static struct pll_init_data main_pll_config = {MAIN_PLL, 100, 1, 4};
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static struct pll_init_data tetris_pll_config = {TETRIS_PLL, 100, 1, 4};
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static struct pll_init_data uart_pll_config = {UART_PLL, 64, 1, 4};
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static struct pll_init_data nss_pll_config = {NSS_PLL, 250, 3, 2};
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static struct pll_init_data ddr3_pll_config = {DDR3A_PLL, 250, 3, 10};
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struct pll_init_data *get_pll_init_data(int pll)
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{
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struct pll_init_data *data = NULL;
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switch (pll) {
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case MAIN_PLL:
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data = &main_pll_config;
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break;
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case TETRIS_PLL:
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data = &tetris_pll_config;
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break;
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case NSS_PLL:
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data = &nss_pll_config;
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break;
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case UART_PLL:
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data = &uart_pll_config;
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break;
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case DDR3_PLL:
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data = &ddr3_pll_config;
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break;
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default:
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data = NULL;
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}
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return data;
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}
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s16 divn_val[16] = {
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-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1
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};
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#ifdef CONFIG_BOARD_EARLY_INIT_F
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int board_early_init_f(void)
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{
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init_plls();
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k2g_mux_config();
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return 0;
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}
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#endif
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#ifdef CONFIG_SPL_BUILD
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void spl_init_keystone_plls(void)
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{
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init_plls();
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}
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#endif
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#ifdef CONFIG_DRIVER_TI_KEYSTONE_NET
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struct eth_priv_t eth_priv_cfg[] = {
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{
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.int_name = "K2G_EMAC",
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.rx_flow = 0,
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.phy_addr = 0,
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.slave_port = 1,
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.sgmii_link_type = SGMII_LINK_MAC_PHY,
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.phy_if = PHY_INTERFACE_MODE_RGMII,
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},
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};
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int get_num_eth_ports(void)
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{
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return sizeof(eth_priv_cfg) / sizeof(struct eth_priv_t);
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}
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#endif
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