upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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68 lines
1.1 KiB
68 lines
1.1 KiB
/*
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* (C) Copyright 2004, Psyent Corporation <www.psyent.com>
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* Scott McNutt <smcnutt@psyent.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <config.h>
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.text
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.global flush_dcache
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flush_dcache:
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add r5, r5, r4
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movhi r8, %hi(CONFIG_SYS_DCACHELINE_SIZE)
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ori r8, r8, %lo(CONFIG_SYS_DCACHELINE_SIZE)
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0: flushd 0(r4)
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add r4, r4, r8
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bltu r4, r5, 0b
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ret
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.global flush_icache
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flush_icache:
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add r5, r5, r4
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movhi r8, %hi(CONFIG_SYS_ICACHELINE_SIZE)
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ori r8, r8, %lo(CONFIG_SYS_ICACHELINE_SIZE)
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1: flushi r4
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add r4, r4, r8
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bltu r4, r5, 1b
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ret
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.global flush_dcache_range
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flush_dcache_range:
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movhi r8, %hi(CONFIG_SYS_DCACHELINE_SIZE)
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ori r8, r8, %lo(CONFIG_SYS_DCACHELINE_SIZE)
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0: flushd 0(r4)
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add r4, r4, r8
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bltu r4, r5, 0b
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ret
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.global flush_cache
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flush_cache:
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add r5, r5, r4
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mov r9, r4
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mov r10, r5
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movhi r8, %hi(CONFIG_SYS_DCACHELINE_SIZE)
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ori r8, r8, %lo(CONFIG_SYS_DCACHELINE_SIZE)
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0: flushd 0(r4)
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add r4, r4, r8
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bltu r4, r5, 0b
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mov r4, r9
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mov r5, r10
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movhi r8, %hi(CONFIG_SYS_ICACHELINE_SIZE)
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ori r8, r8, %lo(CONFIG_SYS_ICACHELINE_SIZE)
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1: flushi r4
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add r4, r4, r8
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bltu r4, r5, 1b
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sync
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flushp
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ret
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