upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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388 lines
9.0 KiB
388 lines
9.0 KiB
/*
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* Copyright (C) 2012 - 2013 Atmel Corporation
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* Bo Shen <voice.shen@atmel.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <mmc.h>
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#include <asm/io.h>
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#include <asm/arch/sama5d3_smc.h>
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#include <asm/arch/at91_common.h>
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#include <asm/arch/at91_pmc.h>
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#include <asm/arch/at91_rstc.h>
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#include <asm/arch/gpio.h>
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#include <asm/arch/clk.h>
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#include <lcd.h>
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#include <atmel_lcdc.h>
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#include <atmel_mci.h>
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#include <micrel.h>
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#include <net.h>
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#include <netdev.h>
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#include <spl.h>
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#include <asm/arch/atmel_mpddrc.h>
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#include <asm/arch/at91_wdt.h>
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#ifdef CONFIG_USB_GADGET_ATMEL_USBA
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#include <asm/arch/atmel_usba_udc.h>
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#endif
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DECLARE_GLOBAL_DATA_PTR;
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/* ------------------------------------------------------------------------- */
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/*
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* Miscelaneous platform dependent initialisations
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*/
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#ifdef CONFIG_NAND_ATMEL
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void sama5d3xek_nand_hw_init(void)
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{
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struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
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at91_periph_clk_enable(ATMEL_ID_SMC);
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/* Configure SMC CS3 for NAND/SmartMedia */
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writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(1) |
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AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(1),
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&smc->cs[3].setup);
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writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(5) |
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AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(5),
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&smc->cs[3].pulse);
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writel(AT91_SMC_CYCLE_NWE(8) | AT91_SMC_CYCLE_NRD(8),
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&smc->cs[3].cycle);
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writel(AT91_SMC_TIMINGS_TCLR(3) | AT91_SMC_TIMINGS_TADL(10) |
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AT91_SMC_TIMINGS_TAR(3) | AT91_SMC_TIMINGS_TRR(4) |
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AT91_SMC_TIMINGS_TWB(5) | AT91_SMC_TIMINGS_RBNSEL(3)|
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AT91_SMC_TIMINGS_NFSEL(1), &smc->cs[3].timings);
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writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
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AT91_SMC_MODE_EXNW_DISABLE |
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#ifdef CONFIG_SYS_NAND_DBW_16
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AT91_SMC_MODE_DBW_16 |
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#else /* CONFIG_SYS_NAND_DBW_8 */
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AT91_SMC_MODE_DBW_8 |
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#endif
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AT91_SMC_MODE_TDF_CYCLE(3),
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&smc->cs[3].mode);
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}
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#endif
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#ifdef CONFIG_CMD_USB
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static void sama5d3xek_usb_hw_init(void)
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{
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at91_set_pio_output(AT91_PIO_PORTD, 25, 0);
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at91_set_pio_output(AT91_PIO_PORTD, 26, 0);
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at91_set_pio_output(AT91_PIO_PORTD, 27, 0);
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}
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#endif
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#ifdef CONFIG_GENERIC_ATMEL_MCI
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static void sama5d3xek_mci_hw_init(void)
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{
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at91_mci_hw_init();
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at91_set_pio_output(AT91_PIO_PORTB, 10, 0); /* MCI0 Power */
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}
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#endif
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#ifdef CONFIG_LCD
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vidinfo_t panel_info = {
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.vl_col = 800,
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.vl_row = 480,
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.vl_clk = 24000000,
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.vl_sync = ATMEL_LCDC_INVLINE_NORMAL | ATMEL_LCDC_INVFRAME_NORMAL,
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.vl_bpix = LCD_BPP,
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.vl_tft = 1,
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.vl_hsync_len = 128,
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.vl_left_margin = 64,
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.vl_right_margin = 64,
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.vl_vsync_len = 2,
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.vl_upper_margin = 22,
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.vl_lower_margin = 21,
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.mmio = ATMEL_BASE_LCDC,
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};
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void lcd_enable(void)
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{
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}
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void lcd_disable(void)
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{
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}
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static void sama5d3xek_lcd_hw_init(void)
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{
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gd->fb_base = CONFIG_SAMA5D3_LCD_BASE;
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/* The higher 8 bit of LCD is board related */
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at91_set_c_periph(AT91_PIO_PORTC, 14, 0); /* LCDD16 */
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at91_set_c_periph(AT91_PIO_PORTC, 13, 0); /* LCDD17 */
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at91_set_c_periph(AT91_PIO_PORTC, 12, 0); /* LCDD18 */
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at91_set_c_periph(AT91_PIO_PORTC, 11, 0); /* LCDD19 */
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at91_set_c_periph(AT91_PIO_PORTC, 10, 0); /* LCDD20 */
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at91_set_c_periph(AT91_PIO_PORTC, 15, 0); /* LCDD21 */
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at91_set_c_periph(AT91_PIO_PORTE, 27, 0); /* LCDD22 */
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at91_set_c_periph(AT91_PIO_PORTE, 28, 0); /* LCDD23 */
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/* Configure lower 16 bit of LCD and enable clock */
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at91_lcd_hw_init();
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}
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#ifdef CONFIG_LCD_INFO
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#include <nand.h>
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#include <version.h>
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void lcd_show_board_info(void)
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{
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ulong dram_size;
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uint64_t nand_size;
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int i;
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char temp[32];
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lcd_printf("%s\n", U_BOOT_VERSION);
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lcd_printf("(C) 2013 ATMEL Corp\n");
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lcd_printf("at91@atmel.com\n");
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lcd_printf("%s CPU at %s MHz\n", get_cpu_name(),
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strmhz(temp, get_cpu_clk_rate()));
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dram_size = 0;
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for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
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dram_size += gd->bd->bi_dram[i].size;
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nand_size = 0;
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#ifdef CONFIG_NAND_ATMEL
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for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
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nand_size += nand_info[i].size;
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#endif
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lcd_printf("%ld MB SDRAM, %lld MB NAND\n",
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dram_size >> 20, nand_size >> 20);
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}
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#endif /* CONFIG_LCD_INFO */
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#endif /* CONFIG_LCD */
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int board_early_init_f(void)
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{
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at91_periph_clk_enable(ATMEL_ID_PIOA);
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at91_periph_clk_enable(ATMEL_ID_PIOB);
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at91_periph_clk_enable(ATMEL_ID_PIOC);
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at91_periph_clk_enable(ATMEL_ID_PIOD);
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at91_periph_clk_enable(ATMEL_ID_PIOE);
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at91_seriald_hw_init();
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return 0;
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}
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int board_init(void)
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{
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/* adress of boot parameters */
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gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
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#ifdef CONFIG_NAND_ATMEL
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sama5d3xek_nand_hw_init();
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#endif
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#ifdef CONFIG_CMD_USB
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sama5d3xek_usb_hw_init();
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#endif
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#ifdef CONFIG_USB_GADGET_ATMEL_USBA
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at91_udp_hw_init();
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#endif
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#ifdef CONFIG_GENERIC_ATMEL_MCI
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sama5d3xek_mci_hw_init();
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#endif
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#ifdef CONFIG_ATMEL_SPI
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at91_spi0_hw_init(1 << 0);
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#endif
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#ifdef CONFIG_MACB
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if (has_emac())
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at91_macb_hw_init();
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if (has_gmac())
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at91_gmac_hw_init();
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#endif
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#ifdef CONFIG_LCD
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if (has_lcdc())
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sama5d3xek_lcd_hw_init();
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#endif
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return 0;
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}
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int dram_init(void)
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{
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gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
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CONFIG_SYS_SDRAM_SIZE);
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return 0;
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}
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int board_phy_config(struct phy_device *phydev)
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{
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/* rx data delay */
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ksz9021_phy_extended_write(phydev,
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MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW, 0x2222);
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/* tx data delay */
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ksz9021_phy_extended_write(phydev,
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MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW, 0x2222);
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/* rx/tx clock delay */
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ksz9021_phy_extended_write(phydev,
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MII_KSZ9021_EXT_RGMII_CLOCK_SKEW, 0xf2f4);
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return 0;
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}
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int board_eth_init(bd_t *bis)
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{
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int rc = 0;
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#ifdef CONFIG_MACB
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if (has_emac())
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rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x00);
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if (has_gmac())
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rc = macb_eth_initialize(0, (void *)ATMEL_BASE_GMAC, 0x00);
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#endif
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#ifdef CONFIG_USB_GADGET_ATMEL_USBA
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usba_udc_probe(&pdata);
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#ifdef CONFIG_USB_ETH_RNDIS
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usb_eth_initialize(bis);
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#endif
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#endif
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return rc;
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}
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#ifdef CONFIG_GENERIC_ATMEL_MCI
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int board_mmc_init(bd_t *bis)
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{
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int rc = 0;
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rc = atmel_mci_init((void *)ATMEL_BASE_MCI0);
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return rc;
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}
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#endif
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/* SPI chip select control */
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#ifdef CONFIG_ATMEL_SPI
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#include <spi.h>
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int spi_cs_is_valid(unsigned int bus, unsigned int cs)
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{
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return bus == 0 && cs < 4;
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}
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void spi_cs_activate(struct spi_slave *slave)
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{
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switch (slave->cs) {
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case 0:
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at91_set_pio_output(AT91_PIO_PORTD, 13, 0);
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case 1:
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at91_set_pio_output(AT91_PIO_PORTD, 14, 0);
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case 2:
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at91_set_pio_output(AT91_PIO_PORTD, 15, 0);
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case 3:
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at91_set_pio_output(AT91_PIO_PORTD, 16, 0);
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default:
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break;
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}
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}
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void spi_cs_deactivate(struct spi_slave *slave)
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{
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switch (slave->cs) {
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case 0:
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at91_set_pio_output(AT91_PIO_PORTD, 13, 1);
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case 1:
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at91_set_pio_output(AT91_PIO_PORTD, 14, 1);
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case 2:
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at91_set_pio_output(AT91_PIO_PORTD, 15, 1);
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case 3:
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at91_set_pio_output(AT91_PIO_PORTD, 16, 1);
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default:
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break;
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}
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}
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#endif /* CONFIG_ATMEL_SPI */
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/* SPL */
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#ifdef CONFIG_SPL_BUILD
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void spl_board_init(void)
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{
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#ifdef CONFIG_SYS_USE_MMC
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sama5d3xek_mci_hw_init();
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#elif CONFIG_SYS_USE_NANDFLASH
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sama5d3xek_nand_hw_init();
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#elif CONFIG_SYS_USE_SERIALFLASH
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at91_spi0_hw_init(1 << 0);
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#endif
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}
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static void ddr2_conf(struct atmel_mpddr *ddr2)
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{
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ddr2->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM);
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ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 |
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ATMEL_MPDDRC_CR_NR_ROW_14 |
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ATMEL_MPDDRC_CR_CAS_DDR_CAS3 |
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ATMEL_MPDDRC_CR_ENRDM_ON |
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ATMEL_MPDDRC_CR_NB_8BANKS |
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ATMEL_MPDDRC_CR_NDQS_DISABLED |
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ATMEL_MPDDRC_CR_DECOD_INTERLEAVED |
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ATMEL_MPDDRC_CR_UNAL_SUPPORTED);
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/*
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* As the DDR2-SDRAm device requires a refresh time is 7.8125us
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* when DDR run at 133MHz, so it needs (7.8125us * 133MHz / 10^9) clocks
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*/
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ddr2->rtr = 0x411;
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ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET |
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2 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET |
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2 << ATMEL_MPDDRC_TPR0_TWR_OFFSET |
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8 << ATMEL_MPDDRC_TPR0_TRC_OFFSET |
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2 << ATMEL_MPDDRC_TPR0_TRP_OFFSET |
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2 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET |
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2 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET |
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2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET);
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ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET |
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200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET |
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28 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET |
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26 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET);
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ddr2->tpr2 = (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET |
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2 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET |
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2 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET |
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7 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET |
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8 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET);
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}
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void mem_init(void)
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{
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struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
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struct atmel_mpddr ddr2;
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ddr2_conf(&ddr2);
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/* enable MPDDR clock */
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at91_periph_clk_enable(ATMEL_ID_MPDDRC);
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writel(0x4, &pmc->scer);
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/* DDRAM2 Controller initialize */
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ddr2_init(ATMEL_BASE_DDRCS, &ddr2);
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}
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void at91_pmc_init(void)
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{
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struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
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u32 tmp;
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tmp = AT91_PMC_PLLAR_29 |
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AT91_PMC_PLLXR_PLLCOUNT(0x3f) |
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AT91_PMC_PLLXR_MUL(43) |
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AT91_PMC_PLLXR_DIV(1);
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at91_plla_init(tmp);
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writel(0x3 << 8, &pmc->pllicpr);
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tmp = AT91_PMC_MCKR_MDIV_4 |
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AT91_PMC_MCKR_CSS_PLLA;
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at91_mck_init(tmp);
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}
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#endif
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