upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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475 lines
9.8 KiB
475 lines
9.8 KiB
/*
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* (C) Copyright 2000
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*
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* Hacked for the DB64360 board by Ingo.Assmus@keymile.com
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* extra improvments by Brain Waite
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* for cpci750 by reinhard.arlt@esd-electronics.com
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*/
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#include <common.h>
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#include <mpc8xx.h>
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#include <malloc.h>
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#include <i2c.h>
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#include "../../Marvell/include/mv_gen_reg.h"
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#include "../../Marvell/include/core.h"
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#define I2C_DELAY 100
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#undef DEBUG_I2C
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#ifdef DEBUG_I2C
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#define DP(x) x
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#else
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#define DP(x)
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#endif
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/* Assuming that there is only one master on the bus (us) */
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void i2c_init (int speed, int slaveaddr)
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{
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unsigned int n, m, freq, margin, power;
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unsigned int actualN = 0, actualM = 0;
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unsigned int minMargin = 0xffffffff;
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unsigned int tclk = CONFIG_SYS_TCLK;
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unsigned int i2cFreq = speed; /* 100000 max. Fast mode not supported */
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DP (puts ("i2c_init\n"));
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/* gtI2cMasterInit */
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for (n = 0; n < 8; n++) {
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for (m = 0; m < 16; m++) {
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power = 2 << n; /* power = 2^(n+1) */
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freq = tclk / (10 * (m + 1) * power);
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if (i2cFreq > freq)
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margin = i2cFreq - freq;
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else
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margin = freq - i2cFreq;
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if (margin < minMargin) {
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minMargin = margin;
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actualN = n;
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actualM = m;
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}
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}
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}
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DP (puts ("setup i2c bus\n"));
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/* Setup bus */
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/* gtI2cReset */
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GT_REG_WRITE (I2C_SOFT_RESET, 0);
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asm(" sync");
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GT_REG_WRITE (I2C_CONTROL, 0);
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asm(" sync");
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DP (puts ("set baudrate\n"));
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GT_REG_WRITE (I2C_STATUS_BAUDE_RATE, (actualM << 3) | actualN);
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asm(" sync");
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DP (puts ("udelay...\n"));
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udelay (I2C_DELAY);
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GT_REG_WRITE (I2C_CONTROL, (0x1 << 2) | (0x1 << 6));
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asm(" sync");
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}
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static uchar i2c_select_device (uchar dev_addr, uchar read, int ten_bit)
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{
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unsigned int status, data, bits = 7;
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unsigned int control;
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int count = 0;
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DP (puts ("i2c_select_device\n"));
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/* Output slave address */
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if (ten_bit) {
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bits = 10;
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}
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GT_REG_READ (I2C_CONTROL, &control);
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control |= (0x1 << 2);
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GT_REG_WRITE (I2C_CONTROL, control);
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asm(" sync");
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GT_REG_READ (I2C_CONTROL, &control);
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control |= (0x1 << 5); /* generate the I2C_START_BIT */
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GT_REG_WRITE (I2C_CONTROL, control);
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asm(" sync");
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RESET_REG_BITS (I2C_CONTROL, (0x01 << 3));
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asm(" sync");
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GT_REG_READ (I2C_CONTROL, &status);
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while ((status & 0x08) != 0x08) {
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GT_REG_READ (I2C_CONTROL, &status);
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}
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count = 0;
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GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status);
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while (((status & 0xff) != 0x08) && ((status & 0xff) != 0x10)){
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if (count > 200) {
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#ifdef DEBUG_I2C
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printf ("Failed to set startbit: 0x%02x\n", status);
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#endif
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GT_REG_WRITE (I2C_CONTROL, (0x1 << 4)); /*stop */
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asm(" sync");
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return (status);
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}
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GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status);
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count++;
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}
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DP (puts ("i2c_select_device:write addr byte\n"));
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/* assert the address */
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data = (dev_addr << 1);
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/* set the read bit */
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data |= read;
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GT_REG_WRITE (I2C_DATA, data);
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asm(" sync");
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RESET_REG_BITS (I2C_CONTROL, BIT3);
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asm(" sync");
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GT_REG_READ (I2C_CONTROL, &status);
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while ((status & 0x08) != 0x08) {
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GT_REG_READ (I2C_CONTROL, &status);
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}
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GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status);
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count = 0;
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while (((status & 0xff) != 0x40) && ((status & 0xff) != 0x18)) {
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if (count > 200) {
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#ifdef DEBUG_I2C
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printf ("Failed to write address: 0x%02x\n", status);
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#endif
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GT_REG_WRITE (I2C_CONTROL, (0x1 << 4)); /*stop */
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return (status);
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}
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GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status);
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asm(" sync");
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count++;
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}
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if (bits == 10) {
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printf ("10 bit I2C addressing not yet implemented\n");
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return (0xff);
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}
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return (0);
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}
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static uchar i2c_get_data (uchar * return_data, int len)
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{
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unsigned int data, status;
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int count = 0;
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DP (puts ("i2c_get_data\n"));
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while (len) {
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RESET_REG_BITS (I2C_CONTROL, BIT3);
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asm(" sync");
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/* Get and return the data */
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GT_REG_READ (I2C_CONTROL, &status);
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while ((status & 0x08) != 0x08) {
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GT_REG_READ (I2C_CONTROL, &status);
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}
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GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status);
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count++;
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while ((status & 0xff) != 0x50) {
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if (count > 20) {
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#ifdef DEBUG_I2C
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printf ("Failed to get data len status: 0x%02x\n", status);
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#endif
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GT_REG_WRITE (I2C_CONTROL, (0x1 << 4)); /*stop */
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asm(" sync");
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return 0;
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}
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GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status);
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count++;
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}
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GT_REG_READ (I2C_DATA, &data);
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len--;
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*return_data = (uchar) data;
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return_data++;
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}
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RESET_REG_BITS (I2C_CONTROL, BIT2 | BIT3);
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asm(" sync");
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count = 0;
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GT_REG_READ (I2C_CONTROL, &status);
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while ((status & 0x08) != 0x08) {
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GT_REG_READ (I2C_CONTROL, &status);
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}
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while ((status & 0xff) != 0x58) {
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if (count > 2000) {
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GT_REG_WRITE (I2C_CONTROL, (0x1 << 4)); /*stop */
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return (status);
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}
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GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status);
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count++;
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}
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GT_REG_WRITE (I2C_CONTROL, (0x1 << 4)); /* stop */
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asm(" sync");
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RESET_REG_BITS (I2C_CONTROL, (0x1 << 3));
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asm(" sync");
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return (0);
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}
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static uchar i2c_write_data (unsigned int *data, int len)
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{
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unsigned int status;
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int count;
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unsigned int temp;
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unsigned int *temp_ptr = data;
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DP (puts ("i2c_write_data\n"));
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while (len) {
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count = 0;
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temp = (unsigned int) (*temp_ptr);
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GT_REG_WRITE (I2C_DATA, temp);
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asm(" sync");
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RESET_REG_BITS (I2C_CONTROL, (0x1 << 3));
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asm(" sync");
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GT_REG_READ (I2C_CONTROL, &status);
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while ((status & 0x08) != 0x08) {
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GT_REG_READ (I2C_CONTROL, &status);
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}
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GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status);
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count++;
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while ((status & 0xff) != 0x28) {
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if (count > 200) {
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GT_REG_WRITE (I2C_CONTROL, (0x1 << 4)); /*stop */
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asm(" sync");
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return (status);
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}
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GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status);
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count++;
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}
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len--;
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temp_ptr++;
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}
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return (0);
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}
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static uchar i2c_write_byte (unsigned char *data, int len)
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{
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unsigned int status;
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int count;
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unsigned int temp;
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unsigned char *temp_ptr = data;
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DP (puts ("i2c_write_byte\n"));
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while (len) {
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count = 0;
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/* Set and assert the data */
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temp = *temp_ptr;
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GT_REG_WRITE (I2C_DATA, temp);
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asm(" sync");
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RESET_REG_BITS (I2C_CONTROL, (0x1 << 3));
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asm(" sync");
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GT_REG_READ (I2C_CONTROL, &status);
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while ((status & 0x08) != 0x08) {
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GT_REG_READ (I2C_CONTROL, &status);
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}
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GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status);
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count++;
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while ((status & 0xff) != 0x28) {
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if (count > 200) {
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GT_REG_WRITE (I2C_CONTROL, (0x1 << 4)); /*stop */
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asm(" sync");
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return (status);
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}
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GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status);
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count++;
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}
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len--;
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temp_ptr++;
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}
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return (0);
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}
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static uchar
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i2c_set_dev_offset (uchar dev_addr, unsigned int offset, int ten_bit,
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int alen)
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{
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uchar status;
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unsigned int table[2];
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table[1] = (offset ) & 0x0ff; /* low byte */
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table[0] = (offset >> 8) & 0x0ff; /* high byte */
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DP (puts ("i2c_set_dev_offset\n"));
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status = i2c_select_device (dev_addr, 0, ten_bit);
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if (status) {
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#ifdef DEBUG_I2C
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22 printf ("Failed to select device setting offset: 0x%02x\n",
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status);
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#endif
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return status;
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}
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/* check the address offset length */
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if (alen == 0)
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/* no address offset */
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return (0);
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else if (alen == 1) {
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/* 1 byte address offset */
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status = i2c_write_data (&offset, 1);
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if (status) {
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#ifdef DEBUG_I2C
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printf ("Failed to write data: 0x%02x\n", status);
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#endif
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return status;
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}
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} else if (alen == 2) {
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/* 2 bytes address offset */
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status = i2c_write_data (table, 2);
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if (status) {
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#ifdef DEBUG_I2C
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printf ("Failed to write data: 0x%02x\n", status);
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#endif
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return status;
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}
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} else {
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/* address offset unknown or not supported */
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printf ("Address length offset %d is not supported\n", alen);
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return 1;
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}
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return 0; /* sucessful completion */
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}
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int
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i2c_read (uchar dev_addr, unsigned int offset, int alen, uchar * data,
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int len)
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{
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uchar status = 0;
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unsigned int i2cFreq = CONFIG_SYS_I2C_SPEED;
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DP (puts ("i2c_read\n"));
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/* set the i2c frequency */
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i2c_init (i2cFreq, CONFIG_SYS_I2C_SLAVE);
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status = i2c_set_dev_offset (dev_addr, offset, 0, alen); /* send the slave address + offset */
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if (status) {
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#ifdef DEBUG_I2C
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printf ("Failed to set slave address & offset: 0x%02x\n",
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status);
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#endif
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return status;
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}
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status = i2c_select_device (dev_addr, 1, 0);
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if (status) {
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#ifdef DEBUG_I2C
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printf ("Failed to select device for data read: 0x%02x\n",
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status);
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#endif
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return status;
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}
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status = i2c_get_data (data, len);
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if (status) {
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#ifdef DEBUG_I2C
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printf ("Data not read: 0x%02x\n", status);
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#endif
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return status;
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}
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return 0;
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}
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void i2c_stop (void)
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{
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GT_REG_WRITE (I2C_CONTROL, (0x1 << 4));
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asm(" sync");
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}
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int
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i2c_write (uchar dev_addr, unsigned int offset, int alen, uchar * data,
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int len)
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{
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uchar status = 0;
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unsigned int i2cFreq = CONFIG_SYS_I2C_SPEED;
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DP (puts ("i2c_write\n"));
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/* set the i2c frequency */
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i2c_init (i2cFreq, CONFIG_SYS_I2C_SLAVE);
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status = i2c_set_dev_offset (dev_addr, offset, 0, alen); /* send the slave address + offset */
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if (status) {
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#ifdef DEBUG_I2C
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printf ("Failed to set slave address & offset: 0x%02x\n",
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status);
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#endif
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return status;
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}
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status = i2c_write_byte (data, len); /* write the data */
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if (status) {
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#ifdef DEBUG_I2C
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printf ("Data not written: 0x%02x\n", status);
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#endif
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return status;
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}
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/* issue a stop bit */
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i2c_stop ();
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return 0;
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}
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int i2c_probe (uchar chip)
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{
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#ifdef DEBUG_I2C
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unsigned int i2c_status;
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#endif
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uchar status = 0;
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unsigned int i2cFreq = CONFIG_SYS_I2C_SPEED;
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DP (puts ("i2c_probe\n"));
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/* set the i2c frequency */
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i2c_init (i2cFreq, CONFIG_SYS_I2C_SLAVE);
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status = i2c_set_dev_offset (chip, 0, 0, 0); /* send the slave address + no offset */
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if (status) {
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#ifdef DEBUG_I2C
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printf ("Failed to set slave address: 0x%02x\n", status);
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#endif
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return (int) status;
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}
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#ifdef DEBUG_I2C
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GT_REG_READ (I2C_STATUS_BAUDE_RATE, &i2c_status);
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printf ("address %#x returned %#x\n", chip, i2c_status);
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#endif
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/* issue a stop bit */
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i2c_stop ();
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return 0; /* successful completion */
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}
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