upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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142 lines
3.5 KiB
142 lines
3.5 KiB
/*
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* (C) Copyright 2001-2003
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* Stefan Roese, DENX Software Engineering, sr@denx.de.
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*
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* (C) Copyright 2005-2009
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* Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/processor.h>
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#include <asm/io.h>
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#include <command.h>
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#include <malloc.h>
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DECLARE_GLOBAL_DATA_PTR;
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extern void lxt971_no_sleep(void);
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int board_early_init_f (void)
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{
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/*
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* IRQ 0-15 405GP internally generated; active high; level sensitive
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* IRQ 16 405GP internally generated; active low; level sensitive
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* IRQ 17-24 RESERVED
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* IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
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* IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive
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* IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive
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* IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive
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* IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive
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* IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
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* IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
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*/
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mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
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mtdcr(UIC0ER, 0x00000000); /* disable all ints */
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mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/
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mtdcr(UIC0PR, 0xFFFFFF81); /* set int polarities */
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mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */
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mtdcr(UIC0VCR, 0x00000001); /* set vect base=0, INT0 highest priority */
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mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
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/*
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* EBC Configuration Register:
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* set ready timeout to 512 ebc-clks -> ca. 15 us
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*/
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mtebc (EBC0_CFG, 0xa8400000);
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/*
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* Setup GPIO pins
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*/
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mtdcr(CPC0_CR0, mfdcr(CPC0_CR0) | ((CONFIG_SYS_FPGA_INIT |
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CONFIG_SYS_FPGA_DONE |
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CONFIG_SYS_XEREADY |
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CONFIG_SYS_NONMONARCH |
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CONFIG_SYS_REV1_2) << 5));
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if (!(in_be32((void *)GPIO0_IR) & CONFIG_SYS_REV1_2)) {
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/* rev 1.2 boards */
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mtdcr(CPC0_CR0, mfdcr(CPC0_CR0) | ((CONFIG_SYS_INTA_FAKE |
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CONFIG_SYS_SELF_RST) << 5));
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}
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out_be32((void *)GPIO0_OR, CONFIG_SYS_VPEN);
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/* setup for output */
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out_be32((void *)GPIO0_TCR, CONFIG_SYS_FPGA_PRG | CONFIG_SYS_FPGA_CLK |
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CONFIG_SYS_FPGA_DATA | CONFIG_SYS_XEREADY | CONFIG_SYS_VPEN);
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/*
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* - check if rev1_2 is low, then:
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* - set/reset CONFIG_SYS_INTA_FAKE/CONFIG_SYS_SELF_RST
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* in TCR to assert INTA# or SELFRST#
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*/
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return 0;
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}
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int misc_init_r (void)
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{
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/* adjust flash start and offset */
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gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
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gd->bd->bi_flashoffset = 0;
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/* deassert EREADY# */
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out_be32((void *)GPIO0_OR,
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in_be32((void *)GPIO0_OR) | CONFIG_SYS_XEREADY);
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return (0);
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}
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ushort pmc405_pci_subsys_deviceid(void)
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{
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ulong val;
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val = in_be32((void *)GPIO0_IR);
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if (!(val & CONFIG_SYS_REV1_2)) { /* low=rev1.2 */
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/* check monarch# signal */
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if (val & CONFIG_SYS_NONMONARCH)
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return CONFIG_SYS_PCI_SUBSYS_DEVICEID_NONMONARCH;
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return CONFIG_SYS_PCI_SUBSYS_DEVICEID_MONARCH;
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}
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return CONFIG_SYS_PCI_SUBSYS_DEVICEID_NONMONARCH;
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}
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/*
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* Check Board Identity
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*/
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int checkboard (void)
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{
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ulong val;
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char str[64];
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int i = getenv_f("serial#", str, sizeof(str));
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puts ("Board: ");
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if (i == -1)
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puts ("### No HW ID - assuming PMC405");
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else
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puts(str);
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val = in_be32((void *)GPIO0_IR);
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if (!(val & CONFIG_SYS_REV1_2)) { /* low=rev1.2 */
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puts(" rev1.2 (");
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if (val & CONFIG_SYS_NONMONARCH) /* monarch# signal */
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puts("non-");
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puts("monarch)");
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} else
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puts(" <=rev1.1");
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putc ('\n');
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return 0;
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}
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void reset_phy(void)
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{
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#ifdef CONFIG_LXT971_NO_SLEEP
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/*
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* Disable sleep mode in LXT971
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*/
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lxt971_no_sleep();
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#endif
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}
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