upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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44 lines
2.1 KiB
44 lines
2.1 KiB
#ifndef __csr_h
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#define __csr_h
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/*
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* (C) Copyright 2000
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* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
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* Marius Groeger <mgroeger@sysgo.de>
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*
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* Control and Status Register definitions for the MBX
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*
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*--------------------------------------------------------------------
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* SPDX-License-Identifier: GPL-2.0+
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*/
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/* bits for control register #1 / status register #1 */
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#define CSR1_ETEN 0x80 /* Ethernet Transceiver Enabled */
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#define CSR1_ELEN 0x40 /* Ethernet XCVR in Internal Loopback */
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#define CSR1_EAEN 0x20 /* Auto selection TP/AUI Enabled */
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#define CSR1_TPEN 0x10 /* TP manually selected */
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#define CSR1_FDDIS 0x08 /* Full Duplex Mode disabled */
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#define CSR1_FCTEN 0x04 /* Collision Testing of XCVR disabled */
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#define CSR1_COM1EN 0x02 /* COM1 signals routed to RS232 Transceiver */
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#define CSR1_XCVRDIS 0x01 /* Onboard RS232 Transceiver Disabled */
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/* bits for control register #2 */
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#define CR2_VDDSEL 0xC0 /* PCMCIA Supply Voltage */
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#define CR2_VPPSEL 0x30 /* PCMCIA Programming Voltage */
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#define CR2_BRDFAIL 0x08 /* Board fail */
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#define CR2_SWS1 0x04 /* Software Status #2 LED */
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#define CR2_SWS2 0x02 /* Software Status #2 LED */
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#define CR2_QSPANRST 0x01 /* Reset QSPAN */
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/* bits for status register #2 */
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#define SR2_VDDSEL 0xC0 /* PCMCIA Supply Voltage */
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#define SR2_VPPSEL 0x30 /* PCMCIA Programming Voltage */
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#define SR2_BATGD 0x08 /* Low Voltage indication for onboard bat */
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#define SR2_NVBATGD 0x04 /* Low Voltage indication for NVRAM */
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#define SR2_RDY 0x02 /* Flash programming status bit */
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#define SR2_FT 0x01 /* Reserved for Factory test purposes */
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#define MBX_CSR1 (*((uchar *)CONFIG_SYS_CSR_BASE))
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#define MBX_CSR2 (*((uchar *)CONFIG_SYS_CSR_BASE + 1))
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#endif /* __csr_h */
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