upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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386 lines
10 KiB
386 lines
10 KiB
/*
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* Maintainer : Steve Sakoman <steve@sakoman.com>
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*
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* Derived from Beagle Board, 3430 SDP, and OMAP3EVM code by
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* Richard Woodruff <r-woodruff2@ti.com>
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* Syed Mohammed Khasim <khasim@ti.com>
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* Sunil Kumar <sunilsaini05@gmail.com>
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* Shashi Ranjan <shashiranjanmca05@gmail.com>
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*
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* (C) Copyright 2004-2008
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* Texas Instruments, <www.ti.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <netdev.h>
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#include <twl4030.h>
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#include <linux/mtd/nand.h>
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#include <asm/io.h>
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#include <asm/arch/mmc_host_def.h>
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#include <asm/arch/mux.h>
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#include <asm/arch/mem.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/gpio.h>
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#include <asm/mach-types.h>
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#include "overo.h"
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DECLARE_GLOBAL_DATA_PTR;
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#define TWL4030_I2C_BUS 0
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#define EXPANSION_EEPROM_I2C_BUS 2
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#define EXPANSION_EEPROM_I2C_ADDRESS 0x51
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#define GUMSTIX_SUMMIT 0x01000200
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#define GUMSTIX_TOBI 0x02000200
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#define GUMSTIX_TOBI_DUO 0x03000200
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#define GUMSTIX_PALO35 0x04000200
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#define GUMSTIX_PALO43 0x05000200
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#define GUMSTIX_CHESTNUT43 0x06000200
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#define GUMSTIX_PINTO 0x07000200
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#define GUMSTIX_GALLOP43 0x08000200
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#define ETTUS_USRP_E 0x01000300
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#define GUMSTIX_NO_EEPROM 0xffffffff
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static struct {
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unsigned int device_vendor;
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unsigned char revision;
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unsigned char content;
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char fab_revision[8];
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char env_var[16];
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char env_setting[64];
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} expansion_config;
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#if defined(CONFIG_CMD_NET)
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static void setup_net_chip(void);
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#endif
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/* GPMC definitions for LAN9221 chips on Tobi expansion boards */
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static const u32 gpmc_lan_config[] = {
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NET_LAN9221_GPMC_CONFIG1,
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NET_LAN9221_GPMC_CONFIG2,
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NET_LAN9221_GPMC_CONFIG3,
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NET_LAN9221_GPMC_CONFIG4,
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NET_LAN9221_GPMC_CONFIG5,
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NET_LAN9221_GPMC_CONFIG6,
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/*CONFIG7- computed as params */
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};
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/*
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* Routine: board_init
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* Description: Early hardware init.
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*/
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int board_init(void)
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{
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gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
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/* board id for Linux */
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gd->bd->bi_arch_number = MACH_TYPE_OVERO;
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/* boot param addr */
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gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
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return 0;
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}
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/*
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* Routine: get_board_revision
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* Description: Returns the board revision
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*/
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int get_board_revision(void)
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{
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int revision;
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#ifdef CONFIG_SYS_I2C_OMAP34XX
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unsigned char data;
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/* board revisions <= R2410 connect 4030 irq_1 to gpio112 */
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/* these boards should return a revision number of 0 */
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/* the code below forces a 4030 RTC irq to ensure that gpio112 is low */
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i2c_set_bus_num(TWL4030_I2C_BUS);
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data = 0x01;
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i2c_write(0x4B, 0x29, 1, &data, 1);
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data = 0x0c;
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i2c_write(0x4B, 0x2b, 1, &data, 1);
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i2c_read(0x4B, 0x2a, 1, &data, 1);
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#endif
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if (!gpio_request(112, "") &&
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!gpio_request(113, "") &&
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!gpio_request(115, "")) {
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gpio_direction_input(112);
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gpio_direction_input(113);
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gpio_direction_input(115);
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revision = gpio_get_value(115) << 2 |
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gpio_get_value(113) << 1 |
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gpio_get_value(112);
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} else {
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puts("Error: unable to acquire board revision GPIOs\n");
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revision = -1;
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}
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return revision;
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}
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#ifdef CONFIG_SPL_BUILD
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/*
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* Routine: get_board_mem_timings
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* Description: If we use SPL then there is no x-loader nor config header
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* so we have to setup the DDR timings ourself on both banks.
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*/
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void get_board_mem_timings(struct board_sdrc_timings *timings)
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{
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timings->mr = MICRON_V_MR_165;
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switch (get_board_revision()) {
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case REVISION_0: /* Micron 1286MB/256MB, 1/2 banks of 128MB */
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timings->mcfg = MICRON_V_MCFG_165(128 << 20);
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timings->ctrla = MICRON_V_ACTIMA_165;
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timings->ctrlb = MICRON_V_ACTIMB_165;
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timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
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break;
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case REVISION_1: /* Micron 256MB/512MB, 1/2 banks of 256MB */
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timings->mcfg = MICRON_V_MCFG_200(256 << 20);
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timings->ctrla = MICRON_V_ACTIMA_200;
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timings->ctrlb = MICRON_V_ACTIMB_200;
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timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
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break;
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case REVISION_2: /* Hynix 256MB/512MB, 1/2 banks of 256MB */
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timings->mcfg = HYNIX_V_MCFG_200(256 << 20);
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timings->ctrla = HYNIX_V_ACTIMA_200;
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timings->ctrlb = HYNIX_V_ACTIMB_200;
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timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
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break;
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case REVISION_3: /* Micron 512MB/1024MB, 1/2 banks of 512MB */
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timings->mcfg = MCFG(512 << 20, 15);
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timings->ctrla = MICRON_V_ACTIMA_200;
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timings->ctrlb = MICRON_V_ACTIMB_200;
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timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
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break;
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default:
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timings->mcfg = MICRON_V_MCFG_165(128 << 20);
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timings->ctrla = MICRON_V_ACTIMA_165;
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timings->ctrlb = MICRON_V_ACTIMB_165;
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timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
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}
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}
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#endif
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/*
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* Routine: get_sdio2_config
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* Description: Return information about the wifi module connection
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* Returns 0 if the module connects though a level translator
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* Returns 1 if the module connects directly
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*/
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int get_sdio2_config(void)
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{
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int sdio_direct;
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if (!gpio_request(130, "") && !gpio_request(139, "")) {
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gpio_direction_output(130, 0);
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gpio_direction_input(139);
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sdio_direct = 1;
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gpio_set_value(130, 0);
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if (gpio_get_value(139) == 0) {
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gpio_set_value(130, 1);
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if (gpio_get_value(139) == 1)
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sdio_direct = 0;
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}
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gpio_direction_input(130);
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} else {
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puts("Error: unable to acquire sdio2 clk GPIOs\n");
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sdio_direct = -1;
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}
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return sdio_direct;
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}
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/*
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* Routine: get_expansion_id
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* Description: This function checks for expansion board by checking I2C
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* bus 2 for the availability of an AT24C01B serial EEPROM.
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* returns the device_vendor field from the EEPROM
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*/
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unsigned int get_expansion_id(void)
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{
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i2c_set_bus_num(EXPANSION_EEPROM_I2C_BUS);
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/* return GUMSTIX_NO_EEPROM if eeprom doesn't respond */
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if (i2c_probe(EXPANSION_EEPROM_I2C_ADDRESS) == 1) {
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i2c_set_bus_num(TWL4030_I2C_BUS);
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return GUMSTIX_NO_EEPROM;
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}
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/* read configuration data */
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i2c_read(EXPANSION_EEPROM_I2C_ADDRESS, 0, 1, (u8 *)&expansion_config,
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sizeof(expansion_config));
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i2c_set_bus_num(TWL4030_I2C_BUS);
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return expansion_config.device_vendor;
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}
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/*
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* Routine: misc_init_r
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* Description: Configure board specific parts
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*/
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int misc_init_r(void)
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{
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twl4030_power_init();
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twl4030_led_init(TWL4030_LED_LEDEN_LEDAON | TWL4030_LED_LEDEN_LEDBON);
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#if defined(CONFIG_CMD_NET)
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setup_net_chip();
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#endif
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printf("Board revision: %d\n", get_board_revision());
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switch (get_sdio2_config()) {
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case 0:
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puts("Tranceiver detected on mmc2\n");
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MUX_OVERO_SDIO2_TRANSCEIVER();
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break;
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case 1:
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puts("Direct connection on mmc2\n");
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MUX_OVERO_SDIO2_DIRECT();
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break;
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default:
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puts("Unable to detect mmc2 connection type\n");
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}
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switch (get_expansion_id()) {
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case GUMSTIX_SUMMIT:
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printf("Recognized Summit expansion board (rev %d %s)\n",
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expansion_config.revision,
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expansion_config.fab_revision);
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setenv("defaultdisplay", "dvi");
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break;
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case GUMSTIX_TOBI:
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printf("Recognized Tobi expansion board (rev %d %s)\n",
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expansion_config.revision,
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expansion_config.fab_revision);
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setenv("defaultdisplay", "dvi");
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break;
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case GUMSTIX_TOBI_DUO:
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printf("Recognized Tobi Duo expansion board (rev %d %s)\n",
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expansion_config.revision,
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expansion_config.fab_revision);
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/* second lan chip */
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enable_gpmc_cs_config(gpmc_lan_config, &gpmc_cfg->cs[4],
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0x2B000000, GPMC_SIZE_16M);
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break;
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case GUMSTIX_PALO35:
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printf("Recognized Palo35 expansion board (rev %d %s)\n",
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expansion_config.revision,
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expansion_config.fab_revision);
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setenv("defaultdisplay", "lcd35");
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break;
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case GUMSTIX_PALO43:
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printf("Recognized Palo43 expansion board (rev %d %s)\n",
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expansion_config.revision,
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expansion_config.fab_revision);
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setenv("defaultdisplay", "lcd43");
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break;
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case GUMSTIX_CHESTNUT43:
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printf("Recognized Chestnut43 expansion board (rev %d %s)\n",
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expansion_config.revision,
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expansion_config.fab_revision);
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setenv("defaultdisplay", "lcd43");
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break;
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case GUMSTIX_PINTO:
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printf("Recognized Pinto expansion board (rev %d %s)\n",
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expansion_config.revision,
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expansion_config.fab_revision);
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break;
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case GUMSTIX_GALLOP43:
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printf("Recognized Gallop43 expansion board (rev %d %s)\n",
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expansion_config.revision,
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expansion_config.fab_revision);
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setenv("defaultdisplay", "lcd43");
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break;
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case ETTUS_USRP_E:
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printf("Recognized Ettus Research USRP-E (rev %d %s)\n",
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expansion_config.revision,
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expansion_config.fab_revision);
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MUX_USRP_E();
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setenv("defaultdisplay", "dvi");
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break;
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case GUMSTIX_NO_EEPROM:
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puts("No EEPROM on expansion board\n");
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break;
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default:
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puts("Unrecognized expansion board\n");
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}
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if (expansion_config.content == 1)
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setenv(expansion_config.env_var, expansion_config.env_setting);
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dieid_num_r();
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return 0;
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}
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/*
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* Routine: set_muxconf_regs
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* Description: Setting up the configuration Mux registers specific to the
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* hardware. Many pins need to be moved from protect to primary
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* mode.
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*/
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void set_muxconf_regs(void)
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{
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MUX_OVERO();
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}
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#if defined(CONFIG_CMD_NET)
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/*
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* Routine: setup_net_chip
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* Description: Setting up the configuration GPMC registers specific to the
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* Ethernet hardware.
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*/
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static void setup_net_chip(void)
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{
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struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE;
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/* first lan chip */
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enable_gpmc_cs_config(gpmc_lan_config, &gpmc_cfg->cs[5], 0x2C000000,
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GPMC_SIZE_16M);
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/* Enable off mode for NWE in PADCONF_GPMC_NWE register */
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writew(readw(&ctrl_base ->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe);
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/* Enable off mode for NOE in PADCONF_GPMC_NADV_ALE register */
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writew(readw(&ctrl_base->gpmc_noe) | 0x0E00, &ctrl_base->gpmc_noe);
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/* Enable off mode for ALE in PADCONF_GPMC_NADV_ALE register */
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writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00,
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&ctrl_base->gpmc_nadv_ale);
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/* Make GPIO 64 as output pin and send a magic pulse through it */
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if (!gpio_request(64, "")) {
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gpio_direction_output(64, 0);
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gpio_set_value(64, 1);
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udelay(1);
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gpio_set_value(64, 0);
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udelay(1);
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gpio_set_value(64, 1);
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}
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}
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#endif
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int board_eth_init(bd_t *bis)
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{
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int rc = 0;
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#ifdef CONFIG_SMC911X
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rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
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#endif
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return rc;
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}
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#if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD)
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int board_mmc_init(bd_t *bis)
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{
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return omap_mmc_init(0, 0, 0, -1, -1);
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}
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#endif
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