upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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249 lines
5.7 KiB
249 lines
5.7 KiB
/*
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* Board specific setup info
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*
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* (C) Copyright 2007, mycable GmbH
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* Carsten Schneider <cs@mycable.de>, Alexander Bigga <ab@mycable.de>
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*
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* (C) Copyright 2003, ARM Ltd.
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* Philippe Robin, <philippe.robin@arm.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <config.h>
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#include <version.h>
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#include <asm/macro.h>
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#include <asm/arch/mb86r0x.h>
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#include <generated/asm-offsets.h>
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/* Set up the platform, once the cpu has been initialized */
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.globl lowlevel_init
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lowlevel_init:
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/*
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* Initialize Clock Reset Generator (CRG)
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*/
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ldr r0, =MB86R0x_CRG_BASE
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/* Not change the initial value that is set by external pin.*/
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WAIT_PLL:
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ldr r2, [r0, #CRG_CRPR] /* Wait for PLLREADY */
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tst r2, #MB86R0x_CRG_CRPR_PLLRDY
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beq WAIT_PLL
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/* Set clock gate control */
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ldr r1, =CONFIG_SYS_CRG_CRHA_INIT
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str r1, [r0, #CRG_CRHA]
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ldr r1, =CONFIG_SYS_CRG_CRPA_INIT
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str r1, [r0, #CRG_CRPA]
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ldr r1, =CONFIG_SYS_CRG_CRPB_INIT
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str r1, [r0, #CRG_CRPB]
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ldr r1, =CONFIG_SYS_CRG_CRHB_INIT
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str r1, [r0, #CRG_CRHB]
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ldr r1, =CONFIG_SYS_CRG_CRAM_INIT
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str r1, [r0, #CRG_CRAM]
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/*
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* Initialize External Bus Interface
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*/
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ldr r0, =MB86R0x_MEMC_BASE
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ldr r1, =CONFIG_SYS_MEMC_MCFMODE0_INIT
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str r1, [r0, #MEMC_MCFMODE0]
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ldr r1, =CONFIG_SYS_MEMC_MCFMODE2_INIT
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str r1, [r0, #MEMC_MCFMODE2]
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ldr r1, =CONFIG_SYS_MEMC_MCFMODE4_INIT
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str r1, [r0, #MEMC_MCFMODE4]
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ldr r1, =CONFIG_SYS_MEMC_MCFTIM0_INIT
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str r1, [r0, #MEMC_MCFTIM0]
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ldr r1, =CONFIG_SYS_MEMC_MCFTIM2_INIT
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str r1, [r0, #MEMC_MCFTIM2]
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ldr r1, =CONFIG_SYS_MEMC_MCFTIM4_INIT
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str r1, [r0, #MEMC_MCFTIM4]
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ldr r1, =CONFIG_SYS_MEMC_MCFAREA0_INIT
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str r1, [r0, #MEMC_MCFAREA0]
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ldr r1, =CONFIG_SYS_MEMC_MCFAREA2_INIT
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str r1, [r0, #MEMC_MCFAREA2]
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ldr r1, =CONFIG_SYS_MEMC_MCFAREA4_INIT
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str r1, [r0, #MEMC_MCFAREA4]
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/*
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* Initialize DDR2 Controller
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*/
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/* Wait for PLL LOCK up time or more */
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wait_timer 20
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/*
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* (2) Initialize DDRIF
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*/
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ldr r0, =MB86R0x_DDR2_BASE
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ldr r1, =CONFIG_SYS_DDR2_DRIMS_INIT
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strh r1, [r0, #DDR2_DRIMS]
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/*
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* (3) Wait for 20MCKPs(120nsec) or more
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*/
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wait_timer 20
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/*
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* (4) IRESET/IUSRRST release
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*/
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ldr r0, =MB86R0x_CCNT_BASE
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ldr r1, =CONFIG_SYS_CCNT_CDCRC_INIT_1
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str r1, [r0, #CCNT_CDCRC]
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/*
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* (5) Wait for 20MCKPs(120nsec) or more
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*/
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wait_timer 20
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/*
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* (6) IDLLRST release
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*/
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ldr r0, =MB86R0x_CCNT_BASE
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ldr r1, =CONFIG_SYS_CCNT_CDCRC_INIT_2
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str r1, [r0, #CCNT_CDCRC]
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/*
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* (7+8) Wait for 200us(=200000ns) or more (DDR2 Spec)
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*/
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wait_timer 33536
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/*
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* (9) MCKE ON
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*/
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ldr r0, =MB86R0x_DDR2_BASE
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ldr r1, =CONFIG_SYS_DDR2_DRIC1_INIT
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strh r1, [r0, #DDR2_DRIC1]
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ldr r1, =CONFIG_SYS_DDR2_DRIC2_INIT
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strh r1, [r0, #DDR2_DRIC2]
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ldr r1, =CONFIG_SYS_DDR2_DRCA_INIT
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strh r1, [r0, #DDR2_DRCA]
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ldr r1, =MB86R0x_DDR2_DRCI_INIT
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strh r1, [r0, #DDR2_DRIC]
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/*
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* (10) Initialize SDRAM
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*/
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ldr r1, =MB86R0x_DDR2_DRCI_CMD
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strh r1, [r0, #DDR2_DRIC]
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wait_timer 67 /* 400ns wait */
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ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC1_1
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strh r1, [r0, #DDR2_DRIC1]
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ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC2_1
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strh r1, [r0, #DDR2_DRIC2]
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ldr r1, =MB86R0x_DDR2_DRCI_CMD
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strh r1, [r0, #DDR2_DRIC]
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ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC1_2
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strh r1, [r0, #DDR2_DRIC1]
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ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC2_2
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strh r1, [r0, #DDR2_DRIC2]
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ldr r1, =MB86R0x_DDR2_DRCI_CMD
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strh r1, [r0, #DDR2_DRIC]
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ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC1_3
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strh r1, [r0, #DDR2_DRIC1]
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ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC2_3
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strh r1, [r0, #DDR2_DRIC2]
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ldr r1, =MB86R0x_DDR2_DRCI_CMD
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strh r1, [r0, #DDR2_DRIC]
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ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC1_4
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strh r1, [r0, #DDR2_DRIC1]
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ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC2_4
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strh r1, [r0, #DDR2_DRIC2]
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ldr r1, =MB86R0x_DDR2_DRCI_CMD
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strh r1, [r0, #DDR2_DRIC]
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ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC1_5
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strh r1, [r0, #DDR2_DRIC1]
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ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC2_5
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strh r1, [r0, #DDR2_DRIC2]
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ldr r1, =MB86R0x_DDR2_DRCI_CMD
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strh r1, [r0, #DDR2_DRIC]
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wait_timer 200
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ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC1_6
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strh r1, [r0, #DDR2_DRIC1]
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ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC2_6
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strh r1, [r0, #DDR2_DRIC2]
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ldr r1, =MB86R0x_DDR2_DRCI_CMD
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strh r1, [r0, #DDR2_DRIC]
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ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC1_7
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strh r1, [r0, #DDR2_DRIC1]
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ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC2_7
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strh r1, [r0, #DDR2_DRIC2]
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ldr r1, =MB86R0x_DDR2_DRCI_CMD
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strh r1, [r0, #DDR2_DRIC]
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wait_timer 18 /* 105ns wait */
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ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC1_8
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strh r1, [r0, #DDR2_DRIC1]
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ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC2_8
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strh r1, [r0, #DDR2_DRIC2]
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ldr r1, =MB86R0x_DDR2_DRCI_CMD
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strh r1, [r0, #DDR2_DRIC]
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wait_timer 200 /* MRS to OCD: 200clock */
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ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC1_9
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strh r1, [r0, #DDR2_DRIC1]
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ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC2_9
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strh r1, [r0, #DDR2_DRIC2]
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ldr r1, =MB86R0x_DDR2_DRCI_CMD
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strh r1, [r0, #DDR2_DRIC]
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ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC1_10
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strh r1, [r0, #DDR2_DRIC1]
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ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC2_10
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strh r1, [r0, #DDR2_DRIC2]
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ldr r1, =MB86R0x_DDR2_DRCI_CMD
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strh r1, [r0, #DDR2_DRIC]
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ldr r1, =CONFIG_SYS_DDR2_DRCM_INIT
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strh r1, [r0, #DDR2_DRCM]
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ldr r1, =CONFIG_SYS_DDR2_DRCST1_INIT
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strh r1, [r0, #DDR2_DRCST1]
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ldr r1, =CONFIG_SYS_DDR2_DRCST2_INIT
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strh r1, [r0, #DDR2_DRCST2]
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ldr r1, =CONFIG_SYS_DDR2_DRCR_INIT
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strh r1, [r0, #DDR2_DRCR]
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ldr r1, =CONFIG_SYS_DDR2_DRCF_INIT
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strh r1, [r0, #DDR2_DRCF]
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ldr r1, =CONFIG_SYS_DDR2_DRASR_INIT
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strh r1, [r0, #DDR2_DRASR]
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/*
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* (11) ODT setting
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*/
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ldr r1, =CONFIG_SYS_DDR2_DROBS_INIT
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strh r1, [r0, #DDR2_DROBS]
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ldr r1, =CONFIG_SYS_DDR2_DROABA_INIT
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strh r1, [r0, #DDR2_DROABA]
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ldr r1, =CONFIG_SYS_DDR2_DRIBSODT1_INIT
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strh r1, [r0, #DDR2_DRIBSODT1]
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/*
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* (12) Shift to ODTCONT ON (SDRAM side) and DDR2 usual operation mode
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*/
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ldr r1, =CONFIG_SYS_DDR2_DROS_INIT
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strh r1, [r0, #DDR2_DROS]
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ldr r1, =MB86R0x_DDR2_DRCI_NORMAL
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strh r1, [r0, #DDR2_DRIC]
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mov pc, lr
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