upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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193 lines
6.2 KiB
193 lines
6.2 KiB
/*
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* Copyright (C) 2004-2005 Arabella Software Ltd.
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* Yuli Barcohen <yuli@arabellasw.com>
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*
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* Support for Analogue&Micro Adder boards family.
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* Tested on AdderII and Adder87x.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#if !defined(CONFIG_MPC875) && !defined(CONFIG_MPC852T)
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#define CONFIG_MPC875
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#endif
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#define CONFIG_ADDER /* Analogue&Micro Adder board */
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#define CONFIG_SYS_TEXT_BASE 0xFE000000
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#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
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#define CONFIG_BAUDRATE 38400
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#define CONFIG_ETHER_ON_FEC1
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#define CONFIG_ETHER_ON_FEC2
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#define CONFIG_HAS_ETH0
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#define CONFIG_HAS_ETH1
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#if defined(CONFIG_ETHER_ON_FEC1) || defined(CONFIG_ETHER_ON_FEC2)
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#define CONFIG_SYS_DISCOVER_PHY
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#define CONFIG_MII_INIT 1
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#define FEC_ENET
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#endif /* CONFIG_ETHER_ON_FEC || CONFIG_ETHER_ON_FEC2 */
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#define CONFIG_8xx_OSCLK 10000000 /* 10 MHz oscillator on EXTCLK */
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#define CONFIG_8xx_CPUCLK_DEFAULT 50000000
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#define CONFIG_SYS_8xx_CPUCLK_MIN 40000000
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#ifdef CONFIG_MPC852T
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#define CONFIG_SYS_8xx_CPUCLK_MAX 50000000
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#else
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#define CONFIG_SYS_8xx_CPUCLK_MAX 133000000
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#endif /* CONFIG_MPC852T */
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/*
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* BOOTP options
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*/
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#define CONFIG_BOOTP_BOOTFILESIZE
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#define CONFIG_BOOTP_BOOTPATH
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#define CONFIG_BOOTP_GATEWAY
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#define CONFIG_BOOTP_HOSTNAME
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/*
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* Command line configuration.
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*/
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#include <config_cmd_default.h>
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#define CONFIG_CMD_DHCP
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#define CONFIG_CMD_IMMAP
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#define CONFIG_CMD_MII
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#define CONFIG_CMD_PING
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#define CONFIG_BOOTDELAY 5 /* Autoboot after 5 seconds */
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#define CONFIG_BOOTCOMMAND "bootm fe040000" /* Autoboot command */
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#define CONFIG_BOOTARGS "root=/dev/mtdblock1 rw mtdparts=1M(ROM)ro,-(root)"
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#define CONFIG_BZIP2 /* Include support for bzip2 compressed images */
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#undef CONFIG_WATCHDOG /* Disable platform specific watchdog */
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/*-----------------------------------------------------------------------
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* Miscellaneous configurable options
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*/
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#define CONFIG_SYS_HUSH_PARSER
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#define CONFIG_SYS_LONGHELP /* #undef to save memory */
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#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buffer Size */
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#define CONFIG_SYS_MAXARGS 16 /* Max number of command args */
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
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#define CONFIG_SYS_LOAD_ADDR 0x400000 /* Default load address */
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/*-----------------------------------------------------------------------
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* RAM configuration (note that CONFIG_SYS_SDRAM_BASE must be zero)
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*/
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#define CONFIG_SYS_SDRAM_BASE 0x00000000
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#define CONFIG_SYS_SDRAM_MAX_SIZE 0x01000000 /* Up to 16 Mbyte */
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#define CONFIG_SYS_MAMR 0x00002114
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/*
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* 4096 Up to 4096 SDRAM rows
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* 1000 factor s -> ms
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* 32 PTP (pre-divider from MPTPR)
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* 4 Number of refresh cycles per period
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* 64 Refresh cycle in ms per number of rows
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*/
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#define CONFIG_SYS_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64))
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#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
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#define CONFIG_SYS_MEMTEST_END 0x00500000 /* 1 ... 5 MB in SDRAM */
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#define CONFIG_SYS_RESET_ADDRESS 0x09900000
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/*-----------------------------------------------------------------------
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* For booting Linux, the board info and command line data
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* have to be in the first 8 MB of memory, since this is
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* the maximum mapped by the Linux kernel during initialization.
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*/
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#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
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#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 KB for Monitor */
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#ifdef CONFIG_BZIP2
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#define CONFIG_SYS_MALLOC_LEN (2500 << 10) /* Reserve ~2.5 MB for malloc() */
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#else
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#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 KB for malloc() */
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#endif /* CONFIG_BZIP2 */
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/*-----------------------------------------------------------------------
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* Flash organisation
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*/
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#define CONFIG_SYS_FLASH_BASE 0xFE000000
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#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
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#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
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#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* Max number of flash banks */
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#define CONFIG_SYS_MAX_FLASH_SECT 128 /* Max num of sects on one chip */
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/* Environment is in flash */
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#define CONFIG_ENV_IS_IN_FLASH
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#define CONFIG_ENV_SECT_SIZE 0x10000 /* We use one complete sector */
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#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
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#define CONFIG_ENV_OVERWRITE
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#define CONFIG_SYS_OR0_PRELIM 0xFF000774
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#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | BR_PS_16 | BR_MS_GPCM | BR_V)
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#define CONFIG_SYS_DIRECT_FLASH_TFTP
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/*-----------------------------------------------------------------------
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* Internal Memory Map Register
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*/
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#define CONFIG_SYS_IMMR 0xFF000000
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/*-----------------------------------------------------------------------
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* Definitions for initial stack pointer and data area (in DPRAM)
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*/
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#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
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#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
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#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
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#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
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/*-----------------------------------------------------------------------
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* Configuration registers
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*/
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#ifdef CONFIG_WATCHDOG
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#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | \
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SYPCR_SWF | SYPCR_SWE | SYPCR_SWRI | \
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SYPCR_SWP)
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#else
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#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | \
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SYPCR_SWF | SYPCR_SWP)
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#endif /* CONFIG_WATCHDOG */
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#define CONFIG_SYS_SIUMCR (SIUMCR_MLRC01 | SIUMCR_DBGC11)
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/* TBSCR - Time Base Status and Control Register */
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#define CONFIG_SYS_TBSCR (TBSCR_TBF | TBSCR_TBE)
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/* PISCR - Periodic Interrupt Status and Control */
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#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
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/* PLPRCR - PLL, Low-Power, and Reset Control Register */
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/* #define CONFIG_SYS_PLPRCR PLPRCR_TEXPS */
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/* SCCR - System Clock and reset Control Register */
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#define SCCR_MASK SCCR_EBDF11
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#define CONFIG_SYS_SCCR SCCR_RTSEL
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#define CONFIG_SYS_DER 0
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/*-----------------------------------------------------------------------
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* Cache Configuration
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*/
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#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx chips */
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/* pass open firmware flat tree */
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#define CONFIG_OF_LIBFDT 1
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#define CONFIG_OF_BOARD_SETUP 1
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#endif /* __CONFIG_H */
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