upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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407 lines
13 KiB
407 lines
13 KiB
/*
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* (C) Copyright 2001
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* Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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/*
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* board/config.h - configuration options, board specific
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#ifndef __ASSEMBLY__
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#include <galileo/core.h>
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#endif
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#include "../board/evb64260/local.h"
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/*
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* High Level Configuration Options
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* (easy to change)
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*/
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#define CONFIG_P3G4 1 /* this is a P3G4 board */
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#define CONFIG_SYS_GT_6426x GT_64260 /* with a 64260 system controller */
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#define CONFIG_SYS_TEXT_BASE 0xfff00000
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#define CONFIG_BAUDRATE 115200 /* console baudrate = 115200 */
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#undef CONFIG_ECC /* enable ECC support */
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/* #define CONFIG_EVB64260_750CX 1 */ /* Support the EVB-64260-750CX Board */
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/* which initialization functions to call for this board */
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#define CONFIG_MISC_INIT_R 1
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#define CONFIG_BOARD_EARLY_INIT_F 1
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#define CONFIG_SYS_BOARD_NAME "P3G4"
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#undef CONFIG_SYS_HUSH_PARSER
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/*
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* The following defines let you select what serial you want to use
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* for your console driver.
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*
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* to use the MPSC, #define CONFIG_MPSC. If you have wired up another
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* mpsc channel, change CONFIG_MPSC_PORT to the desired value.
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*/
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#define CONFIG_MPSC
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#define CONFIG_MPSC_PORT 0
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/* define this if you want to enable GT MAC filtering */
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#define CONFIG_GT_USE_MAC_HASH_TABLE
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#undef CONFIG_ETHER_PORT_MII /* use RMII */
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#if 0
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#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
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#else
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#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
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#endif
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#define CONFIG_ZERO_BOOTDELAY_CHECK
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#define CONFIG_PREBOOT "echo;" \
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"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
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"echo"
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#undef CONFIG_BOOTARGS
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"netdev=eth0\0" \
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"hostname=p3g4\0" \
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"nfsargs=setenv bootargs root=/dev/nfs rw " \
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"nfsroot=${serverip}:${rootpath}\0" \
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"ramargs=setenv bootargs root=/dev/ram rw\0" \
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"addip=setenv bootargs ${bootargs} " \
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"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
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":${hostname}:${netdev}:off panic=1\0" \
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"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
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"flash_nfs=run nfsargs addip addtty;" \
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"bootm ${kernel_addr}\0" \
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"flash_self=run ramargs addip addtty;" \
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"bootm ${kernel_addr} ${ramdisk_addr}\0" \
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"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
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"bootm\0" \
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"rootpath=/opt/eldk/ppc_74xx\0" \
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"bootfile=/tftpboot/p3g4/uImage\0" \
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"kernel_addr=ff000000\0" \
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"ramdisk_addr=ff010000\0" \
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"load=tftp 100000 /tftpboot/p3g4/u-boot.bin\0" \
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"update=protect off fff00000 fff3ffff;era fff00000 fff3ffff;" \
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"cp.b 100000 fff00000 ${filesize};" \
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"setenv filesize;saveenv\0" \
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"upd=run load update\0" \
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""
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#define CONFIG_BOOTCOMMAND "run flash_self"
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#define CONFIG_LOADS_ECHO 0 /* echo off for serial download */
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#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate changes */
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#undef CONFIG_WATCHDOG /* watchdog disabled */
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#undef CONFIG_ALTIVEC /* undef to disable */
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/*
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* BOOTP options
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*/
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#define CONFIG_BOOTP_SUBNETMASK
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#define CONFIG_BOOTP_GATEWAY
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#define CONFIG_BOOTP_HOSTNAME
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#define CONFIG_BOOTP_BOOTPATH
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#define CONFIG_BOOTP_BOOTFILESIZE
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#define CONFIG_TIMESTAMP /* Print image info with timestamp */
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/*
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* Command line configuration.
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*/
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#include <config_cmd_default.h>
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#define CONFIG_CMD_ASKENV
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#define CONFIG_CMD_DHCP
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#define CONFIG_CMD_PCI
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#define CONFIG_CMD_ELF
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#define CONFIG_CMD_MII
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#define CONFIG_CMD_PING
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#define CONFIG_CMD_UNIVERSE
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#define CONFIG_CMD_BSP
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/*
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* Miscellaneous configurable options
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*/
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#define CONFIG_SYS_LONGHELP /* undef to save memory */
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#if defined(CONFIG_CMD_KGDB)
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#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
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#else
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#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
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#endif
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
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#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
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#define CONFIG_SYS_MEMTEST_START 0x00400000 /* memtest works on */
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#define CONFIG_SYS_MEMTEST_END 0x00C00000 /* 4 ... 12 MB in DRAM */
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#define CONFIG_SYS_LOAD_ADDR 0x00300000 /* default load address */
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#define CONFIG_SYS_BUS_CLK 133000000 /* 133 MHz */
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#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
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/*
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* Low Level Configuration Settings
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* (address mappings, register initial values, etc.)
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* You should know what you are doing if you make changes here.
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*/
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/*-----------------------------------------------------------------------
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* Definitions for initial stack pointer and data area
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*/
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#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
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#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
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#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
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#define CONFIG_SYS_INIT_RAM_LOCK
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/*-----------------------------------------------------------------------
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* Start addresses for the final memory configuration
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* (Set up by the startup code)
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* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
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*/
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#define CONFIG_SYS_SDRAM_BASE 0x00000000
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#define CONFIG_SYS_FLASH_BASE 0xff000000
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#define CONFIG_SYS_RESET_ADDRESS 0xfff00100
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#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
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#define CONFIG_SYS_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc */
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/* areas to map different things with the GT in physical space */
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#define CONFIG_SYS_DRAM_BANKS 1
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#define CONFIG_SYS_DFL_GT_REGS 0x14000000 /* boot time GT_REGS */
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/* What to put in the bats. */
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#define CONFIG_SYS_MISC_REGION_BASE 0xf0000000
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/* Peripheral Device section */
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#define CONFIG_SYS_GT_REGS 0xf8000000
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#define CONFIG_SYS_DEV_BASE 0xff000000
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#define CONFIG_SYS_DEV0_SPACE CONFIG_SYS_DEV_BASE
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#define CONFIG_SYS_DEV1_SPACE (CONFIG_SYS_DEV0_SPACE + CONFIG_SYS_DEV0_SIZE)
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#define CONFIG_SYS_DEV2_SPACE (CONFIG_SYS_DEV1_SPACE + CONFIG_SYS_DEV1_SIZE)
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#define CONFIG_SYS_DEV3_SPACE (CONFIG_SYS_DEV2_SPACE + CONFIG_SYS_DEV2_SIZE)
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#define CONFIG_SYS_DEV0_SIZE _8M /* Flash bank */
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#define CONFIG_SYS_DEV1_SIZE 0 /* unused */
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#define CONFIG_SYS_DEV2_SIZE 0 /* unused */
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#define CONFIG_SYS_DEV3_SIZE 0 /* unused */
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#define CONFIG_SYS_16BIT_BOOT_PAR 0xc01b5e7c
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#define CONFIG_SYS_DEV0_PAR CONFIG_SYS_16BIT_BOOT_PAR
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#if 0 /* Wrong?? NTL */
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#define CONFIG_SYS_MPP_CONTROL_0 0x53541717 /* InitAct EOT[4] DBurst TCEn[1] */
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/* DMAAck[1:0] GNT0[1:0] */
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#else
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#define CONFIG_SYS_MPP_CONTROL_0 0x53547777 /* InitAct EOT[4] DBurst TCEn[1] */
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/* REQ0[1:0] GNT0[1:0] */
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#endif
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#define CONFIG_SYS_MPP_CONTROL_1 0x44009911 /* TCEn[4] TCTcnt[4] GPP[13:12] */
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/* DMAReq[4] DMAAck[4] WDNMI WDE */
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#if 0 /* Wrong?? NTL */
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#define CONFIG_SYS_MPP_CONTROL_2 0x40091818 /* TCTcnt[0] GPP[22:21] BClkIn */
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/* DMAAck[1:0] GNT1[1:0] */
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#else
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#define CONFIG_SYS_MPP_CONTROL_2 0x40098888 /* TCTcnt[0] */
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/* GPP[22] (RS232IntB or PCI1Int) */
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/* GPP[21] (RS323IntA) */
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/* BClkIn */
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/* REQ1[1:0] GNT1[1:0] */
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#endif
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#if 0 /* Wrong?? NTL */
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# define CONFIG_SYS_MPP_CONTROL_3 0x00090066 /* GPP[31:29] BClkOut0 */
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/* GPP[27:26] Int[1:0] */
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#else
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# define CONFIG_SYS_MPP_CONTROL_3 0x22090066 /* MREQ MGNT */
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/* GPP[29] (PCI1Int) */
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/* BClkOut0 */
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/* GPP[27] (PCI0Int) */
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/* GPP[26] (RtcInt or PCI1Int) */
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/* CPUInt[25:24] */
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#endif
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#define CONFIG_SYS_SERIAL_PORT_MUX 0x00001102 /* 11=MPSC1/MPSC0 02=ETH 0 and 2 RMII */
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#if 0 /* Wrong?? - NTL */
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# define CONFIG_SYS_GPP_LEVEL_CONTROL 0x000002c6
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#else
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# define CONFIG_SYS_GPP_LEVEL_CONTROL 0x2c600000 /* 0010 1100 0110 0000 */
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/* gpp[29] */
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/* gpp[27:26] */
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/* gpp[22:21] */
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# define CONFIG_SYS_SDRAM_CONFIG 0xd8e18200 /* 0x448 */
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/* idmas use buffer 1,1
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comm use buffer 0
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pci use buffer 1,1
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cpu use buffer 0
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normal load (see also ifdef HVL)
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standard SDRAM (see also ifdef REG)
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non staggered refresh */
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/* 31:26 25 23 20 19 18 16 */
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/* 110110 00 111 0 0 00 1 */
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/* refresh_count=0x200
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phisical interleaving disable
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virtual interleaving enable */
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/* 15 14 13:0 */
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/* 1 0 0x200 */
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#endif
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#if 0
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#define CONFIG_SYS_DUART_IO CONFIG_SYS_DEV2_SPACE
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#define CONFIG_SYS_DUART_CHAN 1 /* channel to use for console */
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#endif
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#undef CONFIG_SYS_INIT_CHAN1
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#undef CONFIG_SYS_INIT_CHAN2
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#if 0
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#define SRAM_BASE CONFIG_SYS_DEV0_SPACE
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#define SRAM_SIZE 0x00100000 /* 1 MB of sram */
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#endif
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/*-----------------------------------------------------------------------
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* PCI stuff
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*-----------------------------------------------------------------------
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*/
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#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */
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#define PCI_HOST_FORCE 1 /* configure as pci host */
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#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
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#define CONFIG_PCI /* include pci support */
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#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
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#define CONFIG_PCI_PNP /* do pci plug-and-play */
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/* PCI MEMORY MAP section */
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#define CONFIG_SYS_PCI0_MEM_BASE 0x80000000
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#define CONFIG_SYS_PCI0_MEM_SIZE _128M
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#define CONFIG_SYS_PCI0_0_MEM_SPACE (CONFIG_SYS_PCI0_MEM_BASE)
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#define CONFIG_SYS_PCI1_MEM_BASE 0x88000000
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#define CONFIG_SYS_PCI1_MEM_SIZE _128M
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#define CONFIG_SYS_PCI1_0_MEM_SPACE (CONFIG_SYS_PCI1_MEM_BASE)
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/* PCI I/O MAP section */
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#define CONFIG_SYS_PCI0_IO_BASE 0xfa000000
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#define CONFIG_SYS_PCI0_IO_SIZE _16M
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#define CONFIG_SYS_PCI0_IO_SPACE (CONFIG_SYS_PCI0_IO_BASE)
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#define CONFIG_SYS_PCI0_IO_SPACE_PCI 0x00000000
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#define CONFIG_SYS_PCI1_IO_BASE 0xfb000000
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#define CONFIG_SYS_PCI1_IO_SIZE _16M
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#define CONFIG_SYS_PCI1_IO_SPACE (CONFIG_SYS_PCI1_IO_BASE)
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#define CONFIG_SYS_PCI1_IO_SPACE_PCI 0x00000000
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/*----------------------------------------------------------------------
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* Initial BAT mappings
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*/
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/* NOTES:
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* 1) GUARDED and WRITE_THRU not allowed in IBATS
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* 2) CACHEINHIBIT and WRITETHROUGH not allowed together in same BAT
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*/
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/* SDRAM */
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#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
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#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
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#define CONFIG_SYS_DBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
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#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
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/* init ram */
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#define CONFIG_SYS_IBAT1L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
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#define CONFIG_SYS_IBAT1U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
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#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
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#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
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/* PCI0, PCI1 in one BAT */
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#define CONFIG_SYS_IBAT2L BATL_NO_ACCESS
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#define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U
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#define CONFIG_SYS_DBAT2L (CONFIG_SYS_PCI0_MEM_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE)
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#define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCI0_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
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/* GT regs, bootrom, all the devices, PCI I/O */
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#define CONFIG_SYS_IBAT3L (CONFIG_SYS_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW)
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#define CONFIG_SYS_IBAT3U (CONFIG_SYS_MISC_REGION_BASE | BATU_VS | BATU_VP | BATU_BL_256M)
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#define CONFIG_SYS_DBAT3L (CONFIG_SYS_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE)
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#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
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/* I2C speed and slave address (for compatability) defaults */
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#define CONFIG_SYS_I2C_SPEED 400000
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#define CONFIG_SYS_I2C_SLAVE 0x7F
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/* I2C addresses for the two DIMM SPD chips */
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#ifndef CONFIG_EVB64260_750CX
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#define DIMM0_I2C_ADDR 0x56
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#define DIMM1_I2C_ADDR 0x54
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#else /* CONFIG_EVB64260_750CX - only has 1 DIMM */
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#define DIMM0_I2C_ADDR 0x54
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#define DIMM1_I2C_ADDR 0x54
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#endif
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/*
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* For booting Linux, the board info and command line data
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* have to be in the first 8 MB of memory, since this is
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* the maximum mapped by the Linux kernel during initialization.
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*/
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#define CONFIG_SYS_BOOTMAPSZ (8<<20) /* Initial Memory map for Linux */
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/*-----------------------------------------------------------------------
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* FLASH organization
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*/
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#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
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#define CONFIG_SYS_MAX_FLASH_SECT 67 /* max number of sectors on one chip */
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#define CONFIG_SYS_EXTRA_FLASH_DEVICE BOOT_DEVICE
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#define CONFIG_SYS_EXTRA_FLASH_WIDTH 2 /* 16 bit */
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#define CONFIG_SYS_BOOT_FLASH_WIDTH 2 /* 16 bit */
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#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
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#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
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#define CONFIG_SYS_FLASH_CFI 1
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#define CONFIG_ENV_IS_IN_FLASH 1
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#define CONFIG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */
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#define CONFIG_ENV_SECT_SIZE 0x20000
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#define CONFIG_ENV_ADDR 0xFFFE0000
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/*-----------------------------------------------------------------------
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* Cache Configuration
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*/
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#define CONFIG_SYS_CACHELINE_SIZE 32 /* For all MPC74xx CPUs */
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#if defined(CONFIG_CMD_KGDB)
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#define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
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#endif
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/*-----------------------------------------------------------------------
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* L2CR setup -- make sure this is right for your board!
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* look in include/74xx_7xx.h for the defines used here
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*/
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#define CONFIG_SYS_L2
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#define L2_INIT (L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \
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L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT)
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#define L2_ENABLE (L2_INIT | L2CR_L2E)
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#define CONFIG_SYS_BOARD_ASM_INIT 1
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#endif /* __CONFIG_H */
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