upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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528 lines
16 KiB
528 lines
16 KiB
/*
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* (C) Copyright 2001-2005
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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/*
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* board/config.h - configuration options, board specific
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#undef CONFIG_SYS_RAMBOOT
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/*
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* High Level Configuration Options
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* (easy to change)
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*/
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#define CONFIG_PM828 1 /* ...on a PM828 module */
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#define CONFIG_CPM2 1 /* Has a CPM2 */
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#ifndef CONFIG_SYS_TEXT_BASE
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#define CONFIG_SYS_TEXT_BASE 0x40000000 /* Standard: boot 64-bit flash */
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#endif
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#undef CONFIG_DB_CR826_J30x_ON /* J30x jumpers on D.B. carrier */
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#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
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#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
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#undef CONFIG_BOOTARGS
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#define CONFIG_BOOTCOMMAND \
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"bootp;" \
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"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
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"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
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"bootm"
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/* enable I2C and select the hardware/software driver */
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#define CONFIG_SYS_I2C
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#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
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#define CONFIG_SYS_I2C_SOFT_SPEED 50000
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#define CONFIG_SYS_I2C_SOFT_SLAVE 0xFE
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/*
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* Software (bit-bang) I2C driver configuration
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*/
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#define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */
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#define I2C_ACTIVE (iop->pdir |= 0x00010000)
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#define I2C_TRISTATE (iop->pdir &= ~0x00010000)
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#define I2C_READ ((iop->pdat & 0x00010000) != 0)
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#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \
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else iop->pdat &= ~0x00010000
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#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \
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else iop->pdat &= ~0x00020000
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#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
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#define CONFIG_RTC_PCF8563
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#define CONFIG_SYS_I2C_RTC_ADDR 0x51
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/*
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* select serial console configuration
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*
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* if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
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* CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
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* for SCC).
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*
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* if CONFIG_CONS_NONE is defined, then the serial console routines must
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* defined elsewhere (for example, on the cogent platform, there are serial
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* ports on the motherboard which are used for the serial console - see
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* cogent/cma101/serial.[ch]).
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*/
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#define CONFIG_CONS_ON_SMC /* define if console on SMC */
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#undef CONFIG_CONS_ON_SCC /* define if console on SCC */
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#undef CONFIG_CONS_NONE /* define if console on something else*/
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#define CONFIG_CONS_INDEX 2 /* which serial channel for console */
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/*
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* select ethernet configuration
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*
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* if CONFIG_ETHER_ON_SCC is selected, then
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* - CONFIG_ETHER_INDEX must be set to the channel number (1-4)
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*
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* if CONFIG_ETHER_ON_FCC is selected, then
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* - one or more CONFIG_ETHER_ON_FCCx (x=1,2,3) must also be selected
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*
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* if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
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* defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
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*/
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#undef CONFIG_ETHER_NONE /* define if ether on something else */
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#undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */
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#define CONFIG_ETHER_INDEX 1 /* which SCC channel for ethernet */
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#define CONFIG_ETHER_ON_FCC /* define if ether on FCC */
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/*
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* - Rx-CLK is CLK11
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* - Tx-CLK is CLK10
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*/
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#define CONFIG_ETHER_ON_FCC1
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# define CONFIG_SYS_CMXFCR_MASK1 (CMXFCR_FC1|CMXFCR_RF1CS_MSK|CMXFCR_TF1CS_MSK)
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#ifndef CONFIG_DB_CR826_J30x_ON
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# define CONFIG_SYS_CMXFCR_VALUE1 (CMXFCR_RF1CS_CLK11|CMXFCR_TF1CS_CLK10)
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#else
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# define CONFIG_SYS_CMXFCR_VALUE1 (CMXFCR_RF1CS_CLK11|CMXFCR_TF1CS_CLK12)
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#endif
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/*
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* - Rx-CLK is CLK15
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* - Tx-CLK is CLK14
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*/
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#define CONFIG_ETHER_ON_FCC2
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# define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
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# define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
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/*
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* - RAM for BD/Buffers is on the 60x Bus (see 28-13)
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* - Enable Full Duplex in FSMR
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*/
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# define CONFIG_SYS_CPMFCR_RAMTYPE 0
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# define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB)
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/* system clock rate (CLKIN) - equal to the 60x and local bus speed */
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#define CONFIG_8260_CLKIN 100000000 /* in Hz */
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#if defined(CONFIG_CONS_NONE) || defined(CONFIG_CONS_USE_EXTC)
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#define CONFIG_BAUDRATE 230400
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#else
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#define CONFIG_BAUDRATE 9600
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#endif
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#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
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#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
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#undef CONFIG_WATCHDOG /* watchdog disabled */
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/*
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* BOOTP options
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*/
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#define CONFIG_BOOTP_SUBNETMASK
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#define CONFIG_BOOTP_GATEWAY
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#define CONFIG_BOOTP_HOSTNAME
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#define CONFIG_BOOTP_BOOTPATH
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#define CONFIG_BOOTP_BOOTFILESIZE
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/*
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* Command line configuration.
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*/
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#include <config_cmd_default.h>
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#define CONFIG_CMD_BEDBUG
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#define CONFIG_CMD_DATE
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#define CONFIG_CMD_DHCP
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#define CONFIG_CMD_EEPROM
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#define CONFIG_CMD_I2C
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#define CONFIG_CMD_NFS
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#define CONFIG_CMD_SNTP
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#ifdef CONFIG_PCI
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#define CONFIG_PCI_INDIRECT_BRIDGE
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#define CONFIG_CMD_PCI
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#endif
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/*
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* Miscellaneous configurable options
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*/
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#define CONFIG_SYS_LONGHELP /* undef to save memory */
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#if defined(CONFIG_CMD_KGDB)
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#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
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#else
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#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
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#endif
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
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#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
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#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
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#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
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#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
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#define CONFIG_SYS_RESET_ADDRESS 0xFDFFFFFC /* "bad" address */
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/*
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* For booting Linux, the board info and command line data
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* have to be in the first 8 MB of memory, since this is
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* the maximum mapped by the Linux kernel during initialization.
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*/
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#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
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/*-----------------------------------------------------------------------
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* Flash and Boot ROM mapping
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*/
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#define CONFIG_SYS_BOOTROM_BASE 0xFF800000
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#define CONFIG_SYS_BOOTROM_SIZE 0x00080000
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#define CONFIG_SYS_FLASH0_BASE 0x40000000
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#define CONFIG_SYS_FLASH0_SIZE 0x02000000
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#define CONFIG_SYS_DOC_BASE 0xFF800000
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#define CONFIG_SYS_DOC_SIZE 0x00100000
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/* Flash bank size (for preliminary settings)
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*/
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#define CONFIG_SYS_FLASH_SIZE CONFIG_SYS_FLASH0_SIZE
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/*-----------------------------------------------------------------------
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* FLASH organization
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*/
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#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */
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#define CONFIG_SYS_MAX_FLASH_SECT 135 /* max num of sects on one chip */
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#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
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#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
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#if 0
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/* Start port with environment in flash; switch to EEPROM later */
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#define CONFIG_ENV_IS_IN_FLASH 1
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#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE+0x40000)
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#define CONFIG_ENV_SIZE 0x40000
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#define CONFIG_ENV_SECT_SIZE 0x40000
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#else
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/* Final version: environment in EEPROM */
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#define CONFIG_ENV_IS_IN_EEPROM 1
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#define CONFIG_SYS_I2C_EEPROM_ADDR 0x58
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#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
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#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4
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#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
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#define CONFIG_ENV_OFFSET 512
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#define CONFIG_ENV_SIZE (2048 - 512)
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#endif
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/*-----------------------------------------------------------------------
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* Hard Reset Configuration Words
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*
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* if you change bits in the HRCW, you must also change the CONFIG_SYS_*
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* defines for the various registers affected by the HRCW e.g. changing
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* HRCW_DPPCxx requires you to also change CONFIG_SYS_SIUMCR.
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*/
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#if defined(CONFIG_BOOT_ROM)
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#define CONFIG_SYS_HRCW_MASTER (HRCW_BPS01 | HRCW_CIP | HRCW_ISB100 | HRCW_BMS)
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#else
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#define CONFIG_SYS_HRCW_MASTER (HRCW_CIP | HRCW_ISB100 | HRCW_BMS)
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#endif
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/* no slaves so just fill with zeros */
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#define CONFIG_SYS_HRCW_SLAVE1 0
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#define CONFIG_SYS_HRCW_SLAVE2 0
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#define CONFIG_SYS_HRCW_SLAVE3 0
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#define CONFIG_SYS_HRCW_SLAVE4 0
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#define CONFIG_SYS_HRCW_SLAVE5 0
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#define CONFIG_SYS_HRCW_SLAVE6 0
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#define CONFIG_SYS_HRCW_SLAVE7 0
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/*-----------------------------------------------------------------------
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* Internal Memory Mapped Register
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*/
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#define CONFIG_SYS_IMMR 0xF0000000
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/*-----------------------------------------------------------------------
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* Definitions for initial stack pointer and data area (in DPRAM)
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*/
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#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
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#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in DPRAM */
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#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
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#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
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/*-----------------------------------------------------------------------
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* Start addresses for the final memory configuration
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* (Set up by the startup code)
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* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
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*
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* 60x SDRAM is mapped at CONFIG_SYS_SDRAM_BASE, local SDRAM
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* is mapped at SDRAM_BASE2_PRELIM.
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*/
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#define CONFIG_SYS_SDRAM_BASE 0x00000000
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#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_FLASH0_BASE
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
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#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
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#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc()*/
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#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
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# define CONFIG_SYS_RAMBOOT
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#endif
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#ifdef CONFIG_PCI
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#define CONFIG_PCI_PNP
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#define CONFIG_EEPRO100
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#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
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#endif
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/*-----------------------------------------------------------------------
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* Cache Configuration
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*/
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#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */
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#if defined(CONFIG_CMD_KGDB)
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# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
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#endif
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/*-----------------------------------------------------------------------
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* HIDx - Hardware Implementation-dependent Registers 2-11
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*-----------------------------------------------------------------------
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* HID0 also contains cache control - initially enable both caches and
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* invalidate contents, then the final state leaves only the instruction
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* cache enabled. Note that Power-On and Hard reset invalidate the caches,
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* but Soft reset does not.
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*
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* HID1 has only read-only information - nothing to set.
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*/
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#define CONFIG_SYS_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\
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HID0_IFEM|HID0_ABE)
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#define CONFIG_SYS_HID0_FINAL (HID0_ICE|HID0_IFEM|HID0_ABE)
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#define CONFIG_SYS_HID2 0
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/*-----------------------------------------------------------------------
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* RMR - Reset Mode Register 5-5
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*-----------------------------------------------------------------------
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* turn on Checkstop Reset Enable
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*/
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#define CONFIG_SYS_RMR RMR_CSRE
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/*-----------------------------------------------------------------------
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* BCR - Bus Configuration 4-25
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*-----------------------------------------------------------------------
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*/
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#define BCR_APD01 0x10000000
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#define CONFIG_SYS_BCR (BCR_APD01|BCR_ETM|BCR_LETM) /* 8260 mode */
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/*-----------------------------------------------------------------------
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* SIUMCR - SIU Module Configuration 4-31
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*-----------------------------------------------------------------------
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*/
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#if 0
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#define CONFIG_SYS_SIUMCR (SIUMCR_DPPC00|SIUMCR_APPC10|SIUMCR_CS10PC01)
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#else
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#define CONFIG_SYS_SIUMCR (SIUMCR_DPPC10|SIUMCR_APPC10)
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#endif
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/*-----------------------------------------------------------------------
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* SYPCR - System Protection Control 4-35
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* SYPCR can only be written once after reset!
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*-----------------------------------------------------------------------
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* Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
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*/
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#if defined(CONFIG_WATCHDOG)
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#define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
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SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
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#else
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#define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
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SYPCR_SWRI|SYPCR_SWP)
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#endif /* CONFIG_WATCHDOG */
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/*-----------------------------------------------------------------------
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* TMCNTSC - Time Counter Status and Control 4-40
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*-----------------------------------------------------------------------
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* Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
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* and enable Time Counter
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*/
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#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
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/*-----------------------------------------------------------------------
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* PISCR - Periodic Interrupt Status and Control 4-42
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*-----------------------------------------------------------------------
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* Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
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* Periodic timer
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*/
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#define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)
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/*-----------------------------------------------------------------------
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* SCCR - System Clock Control 9-8
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*-----------------------------------------------------------------------
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*/
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#define CONFIG_SYS_SCCR (SCCR_DFBRG00)
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/*-----------------------------------------------------------------------
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* RCCR - RISC Controller Configuration 13-7
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*-----------------------------------------------------------------------
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*/
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#define CONFIG_SYS_RCCR 0
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/*
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* Init Memory Controller:
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*
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* Bank Bus Machine PortSz Device
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* ---- --- ------- ------ ------
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* 0 60x GPCM 64 bit FLASH
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* 1 60x SDRAM 64 bit SDRAM
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*
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*/
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/* Initialize SDRAM on local bus
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*/
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#define CONFIG_SYS_INIT_LOCAL_SDRAM
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/* Minimum mask to separate preliminary
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* address ranges for CS[0:2]
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*/
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#define CONFIG_SYS_MIN_AM_MASK 0xC0000000
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/*
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* we use the same values for 32 MB and 128 MB SDRAM
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* refresh rate = 7.68 uS (100 MHz Bus Clock)
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*/
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#define CONFIG_SYS_MPTPR 0x2000
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#define CONFIG_SYS_PSRT 0x16
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#define CONFIG_SYS_MRS_OFFS 0x00000000
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#if defined(CONFIG_BOOT_ROM)
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/*
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* Bank 0 - Boot ROM (8 bit wide)
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*/
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#define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_BOOTROM_BASE & BRx_BA_MSK)|\
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BRx_PS_8 |\
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BRx_MS_GPCM_P |\
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BRx_V)
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#define CONFIG_SYS_OR0_PRELIM (P2SZ_TO_AM(CONFIG_SYS_BOOTROM_SIZE) |\
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ORxG_CSNT |\
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ORxG_ACS_DIV1 |\
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ORxG_SCY_5_CLK |\
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ORxG_EHTR |\
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ORxG_TRLX)
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/*
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* Bank 1 - Flash (64 bit wide)
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*/
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#define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK) |\
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BRx_PS_64 |\
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BRx_MS_GPCM_P |\
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BRx_V)
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#define CONFIG_SYS_OR1_PRELIM (P2SZ_TO_AM(CONFIG_SYS_FLASH_SIZE) |\
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ORxG_CSNT |\
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ORxG_ACS_DIV1 |\
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ORxG_SCY_5_CLK |\
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ORxG_EHTR |\
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ORxG_TRLX)
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#else /* ! CONFIG_BOOT_ROM */
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/*
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* Bank 0 - Flash (64 bit wide)
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*/
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#define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK) |\
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BRx_PS_64 |\
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BRx_MS_GPCM_P |\
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BRx_V)
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#define CONFIG_SYS_OR0_PRELIM (P2SZ_TO_AM(CONFIG_SYS_FLASH_SIZE) |\
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ORxG_CSNT |\
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ORxG_ACS_DIV1 |\
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ORxG_SCY_5_CLK |\
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ORxG_EHTR |\
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ORxG_TRLX)
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/*
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* Bank 1 - Disk-On-Chip
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*/
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#define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_DOC_BASE & BRx_BA_MSK) |\
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BRx_PS_8 |\
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BRx_MS_GPCM_P |\
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BRx_V)
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#define CONFIG_SYS_OR1_PRELIM (P2SZ_TO_AM(CONFIG_SYS_DOC_SIZE) |\
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ORxG_CSNT |\
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ORxG_ACS_DIV1 |\
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ORxG_SCY_5_CLK |\
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ORxG_EHTR |\
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ORxG_TRLX)
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#endif /* CONFIG_BOOT_ROM */
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/* Bank 2 - SDRAM
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*/
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#ifndef CONFIG_SYS_RAMBOOT
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#define CONFIG_SYS_BR2_PRELIM ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK) |\
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BRx_PS_64 |\
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BRx_MS_SDRAM_P |\
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BRx_V)
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/* SDRAM initialization values for 8-column chips
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*/
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#define CONFIG_SYS_OR2_8COL (CONFIG_SYS_MIN_AM_MASK |\
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ORxS_BPD_4 |\
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ORxS_ROWST_PBI0_A9 |\
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ORxS_NUMR_12)
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#define CONFIG_SYS_PSDMR_8COL (PSDMR_SDAM_A13_IS_A5 |\
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PSDMR_BSMA_A14_A16 |\
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PSDMR_SDA10_PBI0_A10 |\
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PSDMR_RFRC_7_CLK |\
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PSDMR_PRETOACT_2W |\
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PSDMR_ACTTORW_2W |\
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PSDMR_LDOTOPRE_1C |\
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PSDMR_WRC_1C |\
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PSDMR_CL_2)
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/* SDRAM initialization values for 9-column chips
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*/
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#define CONFIG_SYS_OR2_9COL (CONFIG_SYS_MIN_AM_MASK |\
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ORxS_BPD_4 |\
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ORxS_ROWST_PBI0_A7 |\
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ORxS_NUMR_13)
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|
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#define CONFIG_SYS_PSDMR_9COL (PSDMR_SDAM_A14_IS_A5 |\
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PSDMR_BSMA_A13_A15 |\
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PSDMR_SDA10_PBI0_A9 |\
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PSDMR_RFRC_7_CLK |\
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PSDMR_PRETOACT_2W |\
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PSDMR_ACTTORW_2W |\
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PSDMR_LDOTOPRE_1C |\
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PSDMR_WRC_1C |\
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PSDMR_CL_2)
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#define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_OR2_9COL
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#define CONFIG_SYS_PSDMR CONFIG_SYS_PSDMR_9COL
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#endif /* CONFIG_SYS_RAMBOOT */
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#endif /* __CONFIG_H */
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