upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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440 lines
12 KiB
440 lines
12 KiB
/*
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* (C) Copyright 2007-2011
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* Heiko Schocher, DENX Software Engineering, hs@denx.de.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*
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* High Level Configuration Options
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* (easy to change)
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*/
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#define CONFIG_MPC8247
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/* MGCOGE */
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#if defined(CONFIG_MGCOGE)
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#define CONFIG_HOSTNAME mgcoge
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#define CONFIG_KM_BOARD_EXTRA_ENV ""
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/* MGCOGE3NE */
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#elif defined(CONFIG_MGCOGE3NE)
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#define CONFIG_HOSTNAME mgcoge3ne
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#define CONFIG_KM_82XX
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#define CONFIG_KM_BOARD_EXTRA_ENV "bobcatreset=true\0"
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#else
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#error ("Board unsupported")
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#endif
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#define CONFIG_SYS_TEXT_BASE 0xFE000000
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/* include common defines/options for all Keymile boards */
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#include "km/keymile-common.h"
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#include "km/km-powerpc.h"
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#define CONFIG_SYS_SDRAM_BASE 0x00000000
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#define CONFIG_SYS_FLASH_BASE 0xFE000000
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#define CONFIG_SYS_FLASH_SIZE 32
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#define CONFIG_SYS_FLASH_CFI
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#define CONFIG_FLASH_CFI_DRIVER
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/* MGCOGE */
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#if defined(CONFIG_MGCOGE)
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#define CONFIG_SYS_MAX_FLASH_BANKS 3
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/* max num of sects on one chip */
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#define CONFIG_SYS_MAX_FLASH_SECT 512
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#define CONFIG_SYS_FLASH_BASE_1 0x50000000
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#define CONFIG_SYS_FLASH_SIZE_1 32
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#define CONFIG_SYS_FLASH_BASE_2 0x52000000
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#define CONFIG_SYS_FLASH_SIZE_2 32
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#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, \
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CONFIG_SYS_FLASH_BASE_1, \
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CONFIG_SYS_FLASH_BASE_2 }
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#define MTDIDS_DEFAULT "nor3=app"
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/*
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* Bank 1 - 60x bus SDRAM
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*/
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#define SDRAM_MAX_SIZE 0x08000000 /* max. 128 MB */
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#define CONFIG_SYS_GLOBAL_SDRAM_LIMIT (256 << 20) /* less than 256 MB */
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/* SDRAM initialization values
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*/
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#define CONFIG_SYS_OR1 ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & \
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ORxS_SDAM_MSK) |\
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ORxS_BPD_8 |\
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ORxS_ROWST_PBI0_A7 |\
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ORxS_NUMR_13)
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#define CONFIG_SYS_PSDMR ( \
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PSDMR_SDAM_A14_IS_A5 |\
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PSDMR_BSMA_A14_A16 |\
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PSDMR_SDA10_PBI0_A9 |\
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PSDMR_RFRC_5_CLK |\
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PSDMR_PRETOACT_2W |\
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PSDMR_ACTTORW_2W |\
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PSDMR_LDOTOPRE_1C |\
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PSDMR_WRC_1C |\
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PSDMR_CL_2)
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/* MGCOGE3NE */
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#elif defined(CONFIG_MGCOGE3NE)
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#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max num of flash banks */
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#define CONFIG_SYS_MAX_FLASH_SECT 1024 /*
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* max num of sects on one
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* chip
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*/
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#define CONFIG_SYS_FLASH_BASE_1 0x50000000
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#define CONFIG_SYS_FLASH_SIZE_1 128
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#define CONFIG_SYS_FLASH_SIZE_2 0 /* dummy value to calc SYS_OR5 */
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#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, \
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CONFIG_SYS_FLASH_BASE_1 }
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#define MTDIDS_DEFAULT "nor2=app"
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/*
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* Bank 1 - 60x bus SDRAM
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* mgcoge3ne has 256MB
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* mgcoge2ne has 128MB
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*/
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#define SDRAM_MAX_SIZE 0x10000000 /* max. 256 MB */
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#define CONFIG_SYS_GLOBAL_SDRAM_LIMIT (512 << 20) /* less than 512 MB */
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#define CONFIG_SYS_OR1 ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & \
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ORxS_SDAM_MSK) |\
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ORxS_BPD_4 |\
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ORxS_NUMR_13 |\
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ORxS_IBID)
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#define CONFIG_SYS_PSDMR ( \
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PSDMR_PBI |\
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PSDMR_RFEN |\
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PSDMR_BSMA_A13_A15 |\
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PSDMR_RFRC_5_CLK |\
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PSDMR_PRETOACT_2W |\
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PSDMR_ACTTORW_2W |\
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PSDMR_LDOTOPRE_1C |\
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PSDMR_WRC_1C |\
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PSDMR_CL_2)
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#define CONFIG_SYS_SDRAM_LIST { \
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{ .size = 256 << 20, \
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.or1 = ORxS_ROWST_PBI1_A4, \
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.psdmr = PSDMR_SDAM_A17_IS_A5 | PSDMR_SDA10_PBI1_A6, \
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}, \
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{ .size = 128 << 20, \
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.or1 = ORxS_ROWST_PBI1_A5, \
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.psdmr = PSDMR_SDAM_A16_IS_A5 | PSDMR_SDA10_PBI1_A7, \
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}, \
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}
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#endif /* defined(CONFIG_MGCOGE3NE) */
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/* include further common stuff for all keymile 82xx boards */
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/*
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* Select serial console configuration
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*
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* If either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
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* CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
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* for SCC).
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*/
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#define CONFIG_CONS_ON_SMC /* Console is on SMC */
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#undef CONFIG_CONS_ON_SCC /* It's not on SCC */
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#undef CONFIG_CONS_NONE /* It's not on external UART */
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#define CONFIG_CONS_INDEX 2 /* SMC2 is used for console */
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#define CONFIG_SYS_SMC_RXBUFLEN 128
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#define CONFIG_SYS_MAXIDLE 10
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/*
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* Select ethernet configuration
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*
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* If either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected,
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* then CONFIG_ETHER_INDEX must be set to the channel number (1-4 for
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* SCC, 1-3 for FCC)
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*
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* If CONFIG_ETHER_NONE is defined, then either the ethernet routines
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* must be defined elsewhere (as for the console), or CONFIG_CMD_NET
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* must be unset.
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*/
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#define CONFIG_ETHER_ON_SCC /* Ethernet is on SCC */
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#undef CONFIG_ETHER_ON_FCC /* Ethernet is not on FCC */
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#undef CONFIG_ETHER_NONE /* No external Ethernet */
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#define CONFIG_ETHER_INDEX 4
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#define CONFIG_HAS_ETH0
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#define CONFIG_SYS_SCC_TOUT_LOOP 10000000
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#define CONFIG_SYS_CMXSCR_VALUE (CMXSCR_RS4CS_CLK7 | CMXSCR_TS4CS_CLK8)
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#ifndef CONFIG_8260_CLKIN
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#define CONFIG_8260_CLKIN 66000000 /* in Hz */
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#endif
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#define BOOTFLASH_START 0xFE000000
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#define CONFIG_KM_CONSOLE_TTY "ttyCPM0"
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#define MTDPARTS_DEFAULT "mtdparts=" \
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"app:" \
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"768k(u-boot)," \
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"128k(env)," \
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"128k(envred)," \
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"3072k(free)," \
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"-(" CONFIG_KM_UBI_PARTITION_NAME_BOOT ")"
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/*
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* Default environment settings
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*/
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#define CONFIG_EXTRA_ENV_SETTINGS \
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CONFIG_KM_BOARD_EXTRA_ENV \
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CONFIG_KM_DEF_ENV \
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"unlock=yes\0" \
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"newenv=" \
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"prot off 0xFE0C0000 +0x40000 && " \
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"era 0xFE0C0000 +0x40000\0" \
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"arch=ppc_82xx\0" \
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""
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
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#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
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#define CONFIG_SYS_RAMBOOT
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#endif
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#define CONFIG_SYS_MONITOR_LEN (768 << 10)
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#define CONFIG_ENV_IS_IN_FLASH
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#ifdef CONFIG_ENV_IS_IN_FLASH
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#define CONFIG_ENV_SECT_SIZE 0x20000
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#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \
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CONFIG_SYS_MONITOR_LEN)
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#define CONFIG_ENV_OFFSET CONFIG_SYS_MONITOR_LEN
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/* Address and size of Redundant Environment Sector */
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#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \
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CONFIG_ENV_SECT_SIZE)
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#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
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#endif /* CONFIG_ENV_IS_IN_FLASH */
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/* enable I2C and select the hardware/software driver */
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#define CONFIG_SYS_I2C
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#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
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#define CONFIG_SYS_I2C_INIT_BOARD
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#define CONFIG_SYS_NUM_I2C_BUSES 3
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#define CONFIG_SYS_I2C_MAX_HOPS 1
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#define CONFIG_SYS_I2C_SOFT_SPEED 50000
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#define CONFIG_SYS_I2C_SPEED CONFIG_SYS_I2C_SOFT_SPEED
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#define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F
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#define CONFIG_SYS_I2C_BUSES {{0, {I2C_NULL_HOP} }, \
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{0, {{I2C_MUX_PCA9542, 0x70, 0} } }, \
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{0, {{I2C_MUX_PCA9542, 0x70, 1} } } }
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#define CONFIG_KM_IVM_BUS 1 /* I2C2 (Mux-Port 1)*/
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#define CONFIG_KM_I2C_ABORT
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/*
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* Software (bit-bang) I2C driver configuration
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*/
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#define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */
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#define I2C_ACTIVE (iop->pdir |= 0x00010000)
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#define I2C_TRISTATE (iop->pdir &= ~0x00010000)
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#define I2C_READ ((iop->pdat & 0x00010000) != 0)
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#define I2C_SDA(bit) do { \
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if (bit) \
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iop->pdat |= 0x00010000; \
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else \
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iop->pdat &= ~0x00010000; \
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} while (0)
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#define I2C_SCL(bit) do { \
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if (bit) \
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iop->pdat |= 0x00020000; \
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else \
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iop->pdat &= ~0x00020000; \
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} while (0)
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#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
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#ifndef __ASSEMBLY__
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void set_sda(int state);
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void set_scl(int state);
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int get_sda(void);
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int get_scl(void);
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#endif
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/* I2C SYSMON (LM75, AD7414 is almost compatible) */
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#define CONFIG_DTT_LM75 /* ON Semi's LM75 */
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#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */
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#define CONFIG_SYS_DTT_MAX_TEMP 70
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#define CONFIG_SYS_DTT_HYSTERESIS 3
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#define CONFIG_SYS_DTT_BUS_NUM 2
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#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
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#define CONFIG_SYS_IMMR 0xF0000000
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#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
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#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* used size in DPRAM */
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#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
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GENERATED_GBL_DATA_SIZE)
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#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
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/* Hard reset configuration word */
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#define CONFIG_SYS_HRCW_MASTER 0x0604b211
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/* No slaves */
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#define CONFIG_SYS_HRCW_SLAVE1 0
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#define CONFIG_SYS_HRCW_SLAVE2 0
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#define CONFIG_SYS_HRCW_SLAVE3 0
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#define CONFIG_SYS_HRCW_SLAVE4 0
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#define CONFIG_SYS_HRCW_SLAVE5 0
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#define CONFIG_SYS_HRCW_SLAVE6 0
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#define CONFIG_SYS_HRCW_SLAVE7 0
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/* Initial Memory map for Linux */
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#define CONFIG_SYS_BOOTMAPSZ (8 << 20)
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#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPUs */
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#if defined(CONFIG_CMD_KGDB)
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# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
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#endif
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#define CONFIG_SYS_HID0_INIT 0
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#define CONFIG_SYS_HID0_FINAL (HID0_ICE | HID0_IFEM | HID0_ABE)
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#define CONFIG_SYS_HID2 0
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#define CONFIG_SYS_SIUMCR 0x4020c200
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#define CONFIG_SYS_SYPCR 0xFFFFFF83
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#define CONFIG_SYS_BCR 0x10000000
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#define CONFIG_SYS_SCCR (SCCR_PCI_MODE | SCCR_PCI_MODCK)
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/*
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*-----------------------------------------------------------------------
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* RMR - Reset Mode Register 5-5
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*-----------------------------------------------------------------------
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* turn on Checkstop Reset Enable
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*/
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#define CONFIG_SYS_RMR 0
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/*
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*-----------------------------------------------------------------------
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* TMCNTSC - Time Counter Status and Control 4-40
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*-----------------------------------------------------------------------
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* Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
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* and enable Time Counter
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*/
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#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
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/*
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*-----------------------------------------------------------------------
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* PISCR - Periodic Interrupt Status and Control 4-42
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*-----------------------------------------------------------------------
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* Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
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* Periodic timer
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*/
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#define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)
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/*
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*-----------------------------------------------------------------------
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* RCCR - RISC Controller Configuration 13-7
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*-----------------------------------------------------------------------
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*/
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#define CONFIG_SYS_RCCR 0
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/*
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* Init Memory Controller:
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*
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* Bank Bus Machine PortSz Device
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* ---- --- ------- ------ ------
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* 0 60x GPCM 8 bit FLASH
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* 1 60x SDRAM 32 bit SDRAM
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* 3 60x GPCM 8 bit GPIO/PIGGY
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* 5 60x GPCM 16 bit CFG-Flash
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*
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*/
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/* Bank 0 - FLASH
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*/
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#define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK) |\
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BRx_PS_8 |\
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BRx_MS_GPCM_P |\
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BRx_V)
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#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) |\
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ORxG_CSNT |\
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ORxG_ACS_DIV2 |\
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ORxG_SCY_5_CLK |\
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ORxG_TRLX)
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#define CONFIG_SYS_MPTPR 0x1800
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/*
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*-----------------------------------------------------------------------------
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* Address for Mode Register Set (MRS) command
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*-----------------------------------------------------------------------------
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*/
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#define CONFIG_SYS_MRS_OFFS 0x00000110
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#define CONFIG_SYS_PSRT 0x0e
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#define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK) |\
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BRx_PS_64 |\
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BRx_MS_SDRAM_P |\
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BRx_V)
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#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR1
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/*
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* UPIO FPGA (GPIO/PIGGY) on CS3 initialization values
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*/
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#define CONFIG_SYS_KMBEC_FPGA_BASE 0x30000000
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#define CONFIG_SYS_KMBEC_FPGA_SIZE 128
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#define CONFIG_SYS_BR3_PRELIM ((CONFIG_SYS_KMBEC_FPGA_BASE & BRx_BA_MSK) |\
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BRx_PS_8 | BRx_MS_GPCM_P | BRx_V)
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#define CONFIG_SYS_OR3_PRELIM (MEG_TO_AM(CONFIG_SYS_KMBEC_FPGA_SIZE) |\
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ORxG_CSNT | ORxG_ACS_DIV2 |\
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ORxG_SCY_3_CLK | ORxG_TRLX)
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/*
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* BFTICU board FPGA on CS4 initialization values
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*/
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#define CONFIG_SYS_FPGA_BASE 0x40000000
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#define CONFIG_SYS_FPGA_SIZE 1 /*1KB*/
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#define CONFIG_SYS_BR4_PRELIM ((CONFIG_SYS_FPGA_BASE & BRx_BA_MSK) |\
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BRx_PS_8 | BRx_MS_GPCM_P | BRx_V)
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#define CONFIG_SYS_OR4_PRELIM (P2SZ_TO_AM(CONFIG_SYS_FPGA_SIZE << 10) |\
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ORxG_CSNT | ORxG_ACS_DIV2 |\
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ORxG_SCY_3_CLK | ORxG_TRLX)
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/*
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* CFG-Flash on CS5 initialization values
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*/
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#define CONFIG_SYS_BR5_PRELIM ((CONFIG_SYS_FLASH_BASE_1 & BRx_BA_MSK) |\
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BRx_PS_16 | BRx_MS_GPCM_P | BRx_V)
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#define CONFIG_SYS_OR5_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE_1 + \
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CONFIG_SYS_FLASH_SIZE_2) |\
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ORxG_CSNT | ORxG_ACS_DIV2 |\
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ORxG_SCY_5_CLK | ORxG_TRLX)
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#define CONFIG_SYS_RESET_ADDRESS 0xFDFFFFFC /* "bad" address */
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/* pass open firmware flat tree */
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#define CONFIG_FIT 1
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#define CONFIG_OF_LIBFDT 1
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#define CONFIG_OF_BOARD_SETUP 1
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#define OF_TBCLK (bd->bi_busfreq / 4)
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#define OF_STDOUT_PATH "/soc/cpm/serial@11a90"
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#endif /* __CONFIG_H */
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