upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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133 lines
3.2 KiB
133 lines
3.2 KiB
/*
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* Copyright (C) Freescale Semiconductor, Inc. 2006. All rights reserved.
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*
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* (C) Copyright 2008
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* Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#if defined(CONFIG_OF_LIBFDT)
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#include <libfdt.h>
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#endif
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#include <pci.h>
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#include <mpc83xx.h>
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#include <fpga.h>
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#include "mvblm7.h"
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#include "fpga.h"
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DECLARE_GLOBAL_DATA_PTR;
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int mvblm7_load_fpga(void)
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{
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size_t data_size = 0;
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void *fpga_data = NULL;
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char *datastr = getenv("fpgadata");
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char *sizestr = getenv("fpgadatasize");
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if (datastr)
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fpga_data = (void *)simple_strtoul(datastr, NULL, 16);
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if (sizestr)
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data_size = (size_t)simple_strtoul(sizestr, NULL, 16);
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return fpga_load(0, fpga_data, data_size);
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}
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static struct pci_region pci_regions[] = {
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{
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bus_start: CFG_PCI1_MEM_BASE,
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phys_start: CFG_PCI1_MEM_PHYS,
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size: CFG_PCI1_MEM_SIZE,
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flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
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},
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{
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bus_start: CFG_PCI1_MMIO_BASE,
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phys_start: CFG_PCI1_MMIO_PHYS,
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size: CFG_PCI1_MMIO_SIZE,
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flags: PCI_REGION_MEM
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},
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{
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bus_start: CFG_PCI1_IO_BASE,
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phys_start: CFG_PCI1_IO_PHYS,
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size: CFG_PCI1_IO_SIZE,
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flags: PCI_REGION_IO
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}
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};
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void pci_init_board(void)
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{
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char *s;
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int i;
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int warmboot;
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int load_fpga;
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volatile immap_t *immr;
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volatile pcictrl83xx_t *pci_ctrl;
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volatile gpio83xx_t *gpio;
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volatile clk83xx_t *clk;
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volatile law83xx_t *pci_law;
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struct pci_region *reg[] = { pci_regions };
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load_fpga = 1;
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immr = (immap_t *) CFG_IMMR;
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clk = (clk83xx_t *) &immr->clk;
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pci_ctrl = immr->pci_ctrl;
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pci_law = immr->sysconf.pcilaw;
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gpio = (volatile gpio83xx_t *)&immr->gpio[0];
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s = getenv("skip_fpga");
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if (s) {
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printf("found 'skip_fpga' -> FPGA _not_ loaded !\n");
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load_fpga = 0;
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}
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gpio->dat = MV_GPIO_DAT;
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gpio->odr = MV_GPIO_ODE;
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if (load_fpga)
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gpio->dir = MV_GPIO_OUT;
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else
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gpio->dir = MV_GPIO_OUT & ~(FPGA_DIN|FPGA_CCLK);
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printf("SICRH / SICRL : 0x%08x / 0x%08x\n", immr->sysconf.sicrh,
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immr->sysconf.sicrl);
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mvblm7_init_fpga();
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if (load_fpga)
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mvblm7_load_fpga();
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/* Enable PCI_CLK_OUTPUTs 0 and 1 with 1:1 clocking */
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clk->occr = 0xc0000000;
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pci_ctrl[0].gcr = 0;
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udelay(2000);
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pci_ctrl[0].gcr = 1;
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for (i = 0; i < 1000; ++i)
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udelay(1000);
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pci_law[0].bar = CFG_PCI1_MEM_PHYS & LAWBAR_BAR;
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pci_law[0].ar = LBLAWAR_EN | LBLAWAR_1GB;
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pci_law[1].bar = CFG_PCI1_IO_PHYS & LAWBAR_BAR;
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pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB;
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warmboot = gd->bd->bi_bootflags & BOOTFLAG_WARM;
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mpc83xx_pci_init(1, reg, warmboot);
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}
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