upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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323 lines
9.1 KiB
323 lines
9.1 KiB
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Configuation settings for the Freescale MCF54418 TWR board.
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*
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* Copyright 2010-2012 Freescale Semiconductor, Inc.
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* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
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*/
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/*
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* board/config.h - configuration options, board specific
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*/
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#ifndef _M54418TWR_H
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#define _M54418TWR_H
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/*
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* High Level Configuration Options
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* (easy to change)
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*/
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#define CONFIG_MCFUART
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#define CONFIG_SYS_UART_PORT (0)
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#define CONFIG_SYS_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
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#define LDS_BOARD_TEXT board/freescale/m54418twr/sbf_dram_init.o (.text*)
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#undef CONFIG_WATCHDOG
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#define CONFIG_TIMESTAMP /* Print image info with timestamp */
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/*
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* BOOTP options
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*/
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#define CONFIG_BOOTP_BOOTFILESIZE
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/*
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* NAND FLASH
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*/
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#ifdef CONFIG_CMD_NAND
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#define CONFIG_JFFS2_NAND
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#define CONFIG_NAND_FSL_NFC
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#define CONFIG_SYS_NAND_BASE 0xFC0FC000
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#define CONFIG_SYS_MAX_NAND_DEVICE 1
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#define NAND_MAX_CHIPS CONFIG_SYS_MAX_NAND_DEVICE
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#define CONFIG_SYS_NAND_SELECT_DEVICE
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#endif
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/* Network configuration */
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#define CONFIG_MCFFEC
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#ifdef CONFIG_MCFFEC
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#define CONFIG_MII_INIT 1
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#define CONFIG_SYS_DISCOVER_PHY
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#define CONFIG_SYS_RX_ETH_BUFFER 2
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#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
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#define CONFIG_SYS_TX_ETH_BUFFER 2
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#define CONFIG_HAS_ETH1
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#define CONFIG_SYS_FEC0_PINMUX 0
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#define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE
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#define CONFIG_SYS_FEC1_PINMUX 0
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#define CONFIG_SYS_FEC1_MIIBASE CONFIG_SYS_FEC0_MIIBASE
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#define MCFFEC_TOUT_LOOP 50000
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#define CONFIG_SYS_FEC0_PHYADDR 0
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#define CONFIG_SYS_FEC1_PHYADDR 1
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#define CONFIG_ETHPRIME "FEC0"
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#define CONFIG_IPADDR 192.168.1.2
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#define CONFIG_NETMASK 255.255.255.0
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#define CONFIG_SERVERIP 192.168.1.1
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#define CONFIG_GATEWAYIP 192.168.1.1
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#define CONFIG_SYS_FEC_BUF_USE_SRAM
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/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
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#ifndef CONFIG_SYS_DISCOVER_PHY
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#define FECDUPLEX FULL
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#define FECSPEED _100BASET
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#define LINKSTATUS 1
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#else
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#define LINKSTATUS 0
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#ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
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#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
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#endif
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#endif /* CONFIG_SYS_DISCOVER_PHY */
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#endif
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#define CONFIG_HOSTNAME "M54418TWR"
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#if defined(CONFIG_CF_SBF)
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/* ST Micro serial flash */
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#define CONFIG_SYS_LOAD_ADDR2 0x40010007
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"netdev=eth0\0" \
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"inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \
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"loadaddr=0x40010000\0" \
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"sbfhdr=sbfhdr.bin\0" \
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"uboot=u-boot.bin\0" \
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"load=tftp ${loadaddr} ${sbfhdr};" \
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"tftp " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${uboot} \0" \
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"upd=run load; run prog\0" \
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"prog=sf probe 0:1 1000000 3;" \
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"sf erase 0 40000;" \
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"sf write ${loadaddr} 0 40000;" \
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"save\0" \
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""
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#elif defined(CONFIG_SYS_NAND_BOOT)
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"netdev=eth0\0" \
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"inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \
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"loadaddr=0x40010000\0" \
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"u-boot=u-boot.bin\0" \
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"load=tftp ${loadaddr} ${u-boot};\0" \
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"upd=run load; run prog\0" \
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"prog=nand device 0;" \
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"nand erase 0 40000;" \
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"nb_update ${loadaddr} ${filesize};" \
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"save\0" \
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""
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#else
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#define CONFIG_SYS_UBOOT_END 0x3FFFF
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"netdev=eth0\0" \
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"inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \
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"loadaddr=40010000\0" \
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"u-boot=u-boot.bin\0" \
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"load=tftp ${loadaddr) ${u-boot}\0" \
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"upd=run load; run prog\0" \
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"prog=prot off mram" " ;" \
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"cp.b ${loadaddr} 0 ${filesize};" \
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"save\0" \
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""
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#endif
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/* Realtime clock */
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#undef CONFIG_MCFRTC
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#define CONFIG_RTC_MCFRRTC
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#define CONFIG_SYS_MCFRRTC_BASE 0xFC0A8000
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/* Timer */
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#define CONFIG_MCFTMR
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#undef CONFIG_MCFPIT
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/* I2c */
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#undef CONFIG_SYS_FSL_I2C
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#undef CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
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/* I2C speed and slave address */
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#define CONFIG_SYS_I2C_SPEED 80000
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#define CONFIG_SYS_I2C_SLAVE 0x7F
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#define CONFIG_SYS_I2C_OFFSET 0x58000
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#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
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/* DSPI and Serial Flash */
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#define CONFIG_CF_DSPI
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#define CONFIG_SERIAL_FLASH
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#define CONFIG_HARD_SPI
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#define CONFIG_SYS_SBFHDR_SIZE 0x7
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#ifdef CONFIG_CMD_SPI
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# define CONFIG_SYS_DSPI_CTAR0 (DSPI_CTAR_TRSZ(7) | \
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DSPI_CTAR_PCSSCK_1CLK | \
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DSPI_CTAR_PASC(0) | \
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DSPI_CTAR_PDT(0) | \
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DSPI_CTAR_CSSCK(0) | \
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DSPI_CTAR_ASC(0) | \
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DSPI_CTAR_DT(1))
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# define CONFIG_SYS_DSPI_CTAR1 (CONFIG_SYS_DSPI_CTAR0)
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# define CONFIG_SYS_DSPI_CTAR2 (CONFIG_SYS_DSPI_CTAR0)
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#endif
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/* Input, PCI, Flexbus, and VCO */
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#define CONFIG_EXTRA_CLOCK
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#define CONFIG_PRAM 2048 /* 2048 KB */
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#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x10000)
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#define CONFIG_SYS_MBAR 0xFC000000
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/*
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* Low Level Configuration Settings
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* (address mappings, register initial values, etc.)
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* You should know what you are doing if you make changes here.
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*/
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/*-----------------------------------------------------------------------
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* Definitions for initial stack pointer and data area (in DPRAM)
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*/
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#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000
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/* End of used area in internal SRAM */
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#define CONFIG_SYS_INIT_RAM_SIZE 0x10000
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#define CONFIG_SYS_INIT_RAM_CTRL 0x221
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#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - \
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GENERATED_GBL_DATA_SIZE) - 32)
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#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
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#define CONFIG_SYS_SBFHDR_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - 32)
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/*-----------------------------------------------------------------------
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* Start addresses for the final memory configuration
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* (Set up by the startup code)
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* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
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*/
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#define CONFIG_SYS_SDRAM_BASE 0x40000000
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#define CONFIG_SYS_SDRAM_SIZE 128 /* SDRAM size in MB */
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#define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + 0x400)
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#define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
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#define CONFIG_SYS_DRAM_TEST
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#if defined(CONFIG_CF_SBF) || defined(CONFIG_SYS_NAND_BOOT)
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#define CONFIG_SERIAL_BOOT
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#endif
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#if defined(CONFIG_SERIAL_BOOT)
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#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE + 0x400)
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#else
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#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
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#endif
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#define CONFIG_SYS_BOOTPARAMS_LEN (64 * 1024)
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/* Reserve 256 kB for Monitor */
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#define CONFIG_SYS_MONITOR_LEN (256 << 10)
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/* Reserve 256 kB for malloc() */
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#define CONFIG_SYS_MALLOC_LEN (256 << 10)
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/*
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* For booting Linux, the board info and command line data
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* have to be in the first 8 MB of memory, since this is
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* the maximum mapped by the Linux kernel during initialization ??
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*/
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/* Initial Memory map for Linux */
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#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + \
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(CONFIG_SYS_SDRAM_SIZE << 20))
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/* Configuration for environment
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* Environment is embedded in u-boot in the second sector of the flash
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*/
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#if !defined(CONFIG_SERIAL_BOOT) /*MRAM boot*/
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#define CONFIG_ENV_ADDR (0x40000 - 0x1000) /*MRAM size 40000*/
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#define CONFIG_ENV_SIZE 0x1000
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#endif
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#if defined(CONFIG_CF_SBF)
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#define CONFIG_ENV_SPI_CS 1
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#define CONFIG_ENV_OFFSET 0x40000
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#define CONFIG_ENV_SIZE 0x2000
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#define CONFIG_ENV_SECT_SIZE 0x10000
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#endif
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#if defined(CONFIG_SYS_NAND_BOOT)
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#define CONFIG_ENV_OFFSET 0x80000
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#define CONFIG_ENV_SIZE 0x20000
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#define CONFIG_ENV_SECT_SIZE 0x20000
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#endif
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#undef CONFIG_ENV_OVERWRITE
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/* FLASH organization */
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#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
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#ifdef CONFIG_SYS_FLASH_CFI
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/* Max size that the board might have */
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#define CONFIG_SYS_FLASH_SIZE 0x1000000
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#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
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/* max number of memory banks */
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#define CONFIG_SYS_MAX_FLASH_BANKS 1
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/* max number of sectors on one chip */
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#define CONFIG_SYS_MAX_FLASH_SECT 270
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/* "Real" (hardware) sectors protection */
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#define CONFIG_SYS_FLASH_CHECKSUM
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#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE }
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#else
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/* max number of sectors on one chip */
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#define CONFIG_SYS_MAX_FLASH_SECT 270
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/* max number of sectors on one chip */
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#define CONFIG_SYS_MAX_FLASH_BANKS 0
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#endif
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/*
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* This is setting for JFFS2 support in u-boot.
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* NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support.
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*/
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#ifdef CONFIG_CMD_JFFS2
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#define CONFIG_JFFS2_DEV "nand0"
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#define CONFIG_JFFS2_PART_OFFSET (0x800000)
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#endif
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/* Cache Configuration */
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#define CONFIG_SYS_CACHELINE_SIZE 16
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#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
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CONFIG_SYS_INIT_RAM_SIZE - 8)
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#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
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CONFIG_SYS_INIT_RAM_SIZE - 4)
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#define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA)
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#define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA)
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#define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE | \
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CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
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CF_ACR_EN | CF_ACR_SM_ALL)
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#define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_IEC | \
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CF_CACR_ICINVA | CF_CACR_EUSP)
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#define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR | \
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CF_CACR_DEC | CF_CACR_DDCM_P | \
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CF_CACR_DCINVA) & ~CF_CACR_ICINVA)
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#define CACR_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
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CONFIG_SYS_INIT_RAM_SIZE - 12)
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/*-----------------------------------------------------------------------
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* Memory bank definitions
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*/
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/*
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* CS0 - NOR Flash 16MB
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* CS1 - Available
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* CS2 - Available
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* CS3 - Available
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* CS4 - Available
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* CS5 - Available
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*/
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/* Flash */
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#define CONFIG_SYS_CS0_BASE 0x00000000
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#define CONFIG_SYS_CS0_MASK 0x000F0101
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#define CONFIG_SYS_CS0_CTRL 0x00001D60
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#endif /* _M54418TWR_H */
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