upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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Topics must start with a letter or number, can include dashes ('-') and can be up to 35 characters long.
242 lines
8.0 KiB
242 lines
8.0 KiB
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2009, STMicroelectronics - All Rights Reserved
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* Author(s): Vipin Kumar, <vipin.kumar@st.com> for STMicroelectronics.
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*
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* Copyright (C) 2012, 2015 Stefan Roese <sr@denx.de>
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*
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* High Level Configuration Options
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* (easy to change)
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*/
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#define CONFIG_SPEAR600 /* SPEAr600 SoC */
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#define CONFIG_X600 /* on X600 board */
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#include <asm/arch/hardware.h>
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/* Timer, HZ specific defines */
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#define CONFIG_SYS_HZ_CLOCK 8300000
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#define CONFIG_SYS_FLASH_BASE 0xf8000000
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/* Reserve 8KiB for SPL */
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#define CONFIG_SPL_PAD_TO 8192 /* decimal for 'dd' */
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#define CONFIG_SYS_SPL_LEN CONFIG_SPL_PAD_TO
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#define CONFIG_SYS_UBOOT_BASE (CONFIG_SYS_FLASH_BASE + \
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CONFIG_SYS_SPL_LEN)
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#define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
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#define CONFIG_SYS_MONITOR_LEN 0x60000
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/* Serial Configuration (PL011) */
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#define CONFIG_SYS_SERIAL0 0xD0000000
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#define CONFIG_SYS_SERIAL1 0xD0080000
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#define CONFIG_PL01x_PORTS { (void *)CONFIG_SYS_SERIAL0, \
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(void *)CONFIG_SYS_SERIAL1 }
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#define CONFIG_PL011_CLOCK (48 * 1000 * 1000)
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#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, \
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57600, 115200 }
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#define CONFIG_SYS_LOADS_BAUD_CHANGE
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/* NOR FLASH config options */
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#define CONFIG_ST_SMI
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#define CONFIG_SYS_MAX_FLASH_BANKS 1
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#define CONFIG_SYS_FLASH_BANK_SIZE 0x01000000
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#define CONFIG_SYS_FLASH_ADDR_BASE { CONFIG_SYS_FLASH_BASE }
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#define CONFIG_SYS_MAX_FLASH_SECT 128
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#define CONFIG_SYS_FLASH_EMPTY_INFO
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#define CONFIG_SYS_FLASH_ERASE_TOUT (3 * CONFIG_SYS_HZ)
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#define CONFIG_SYS_FLASH_WRITE_TOUT (3 * CONFIG_SYS_HZ)
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/* NAND FLASH config options */
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#define CONFIG_NAND_FSMC
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#define CONFIG_SYS_NAND_SELF_INIT
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#define CONFIG_SYS_MAX_NAND_DEVICE 1
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#define CONFIG_SYS_NAND_BASE CONFIG_FSMC_NAND_BASE
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#define CONFIG_MTD_ECC_SOFT
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#define CONFIG_SYS_FSMC_NAND_8BIT
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#define CONFIG_SYS_NAND_ONFI_DETECTION
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#define CONFIG_NAND_ECC_BCH
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/* UBI/UBI config options */
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/* Ethernet config options */
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#define CONFIG_PHY_RESET_DELAY 10000 /* in usec */
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#define CONFIG_SPEAR_GPIO
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/* I2C config options */
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#define CONFIG_SYS_I2C
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#define CONFIG_SYS_I2C_BASE 0xD0200000
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#define CONFIG_SYS_I2C_SPEED 400000
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#define CONFIG_SYS_I2C_SLAVE 0x02
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#define CONFIG_I2C_CHIPADDRESS 0x50
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#define CONFIG_RTC_M41T62 1
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#define CONFIG_SYS_I2C_RTC_ADDR 0x68
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/* FPGA config options */
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#define CONFIG_FPGA_COUNT 1
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/* USB EHCI options */
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#define CONFIG_USB_EHCI_SPEAR
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#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
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/*
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* U-Boot Environment placing definitions.
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*/
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#define CONFIG_ENV_SECT_SIZE 0x00010000
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#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \
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CONFIG_SYS_MONITOR_LEN)
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#define CONFIG_ENV_SIZE 0x02000
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#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + \
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CONFIG_ENV_SECT_SIZE)
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#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
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/* Miscellaneous configurable options */
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#define CONFIG_ARCH_CPU_INIT
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#define CONFIG_BOOT_PARAMS_ADDR 0x00000100
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#define CONFIG_CMDLINE_TAG
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#define CONFIG_SETUP_MEMORY_TAGS
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#define CONFIG_MX_CYCLIC /* enable mdc/mwc commands */
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#define CONFIG_SYS_MEMTEST_START 0x00800000
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#define CONFIG_SYS_MEMTEST_END 0x04000000
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#define CONFIG_SYS_MALLOC_LEN (8 << 20)
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#define CONFIG_SYS_LOAD_ADDR 0x00800000
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#define CONFIG_HOSTNAME "x600"
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#define CONFIG_UBI_PART ubi0
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#define CONFIG_UBIFS_VOLUME rootfs
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"u-boot_addr=1000000\0" \
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"u-boot=" CONFIG_HOSTNAME "/u-boot.spr\0" \
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"load=tftp ${u-boot_addr} ${u-boot}\0" \
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"update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE) \
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" +${filesize};" \
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"erase " __stringify(CONFIG_SYS_MONITOR_BASE) " +${filesize};" \
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"cp.b ${u-boot_addr} " __stringify(CONFIG_SYS_MONITOR_BASE) \
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" ${filesize};" \
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"protect on " __stringify(CONFIG_SYS_MONITOR_BASE) \
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" +${filesize}\0" \
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"upd=run load update\0" \
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"ubifs=" CONFIG_HOSTNAME "/ubifs.img\0" \
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"part=" __stringify(CONFIG_UBI_PART) "\0" \
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"vol=" __stringify(CONFIG_UBIFS_VOLUME) "\0" \
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"load_ubifs=tftp ${kernel_addr} ${ubifs}\0" \
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"update_ubifs=ubi part ${part};ubi write ${kernel_addr} ${vol}" \
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" ${filesize}\0" \
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"upd_ubifs=run load_ubifs update_ubifs\0" \
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"init_ubifs=nand erase.part ubi0;ubi part ${part};" \
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"ubi create ${vol} 4000000\0" \
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"netdev=eth0\0" \
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"rootpath=/opt/eldk-4.2/arm\0" \
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"nfsargs=setenv bootargs root=/dev/nfs rw " \
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"nfsroot=${serverip}:${rootpath}\0" \
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"ramargs=setenv bootargs root=/dev/ram rw\0" \
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"boot_part=0\0" \
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"altbootcmd=if test $boot_part -eq 0;then " \
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"echo Switching to partition 1!;" \
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"setenv boot_part 1;" \
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"else; " \
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"echo Switching to partition 0!;" \
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"setenv boot_part 0;" \
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"fi;" \
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"saveenv;boot\0" \
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"ubifsargs=set bootargs ubi.mtd=ubi${boot_part} " \
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"root=ubi0:rootfs rootfstype=ubifs\0" \
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"kernel=" CONFIG_HOSTNAME "/uImage\0" \
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"kernel_fs=/boot/uImage \0" \
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"kernel_addr=1000000\0" \
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"dtb=" CONFIG_HOSTNAME "/" \
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CONFIG_HOSTNAME ".dtb\0" \
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"dtb_fs=/boot/" CONFIG_HOSTNAME ".dtb\0" \
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"dtb_addr=1800000\0" \
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"load_kernel=tftp ${kernel_addr} ${kernel}\0" \
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"load_dtb=tftp ${dtb_addr} ${dtb}\0" \
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"addip=setenv bootargs ${bootargs} " \
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"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
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":${hostname}:${netdev}:off panic=1\0" \
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"addcon=setenv bootargs ${bootargs} console=ttyAMA0," \
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"${baudrate}\0" \
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"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
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"net_nfs=run load_dtb load_kernel; " \
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"run nfsargs addip addcon addmtd addmisc;" \
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"bootm ${kernel_addr} - ${dtb_addr}\0" \
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"mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \
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"mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
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"nand_ubifs=run ubifs_mount ubifs_load ubifsargs addip" \
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" addcon addmisc addmtd;" \
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"bootm ${kernel_addr} - ${dtb_addr}\0" \
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"ubifs_mount=ubi part ubi${boot_part};ubifsmount ubi:rootfs\0" \
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"ubifs_load=ubifsload ${kernel_addr} ${kernel_fs};" \
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"ubifsload ${dtb_addr} ${dtb_fs};\0" \
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"nand_ubifs=run ubifs_mount ubifs_load ubifsargs addip addcon " \
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"addmtd addmisc;bootm ${kernel_addr} - ${dtb_addr}\0" \
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"bootcmd=run nand_ubifs\0" \
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"\0"
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/* Physical Memory Map */
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#define PHYS_SDRAM_1 0x00000000
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#define PHYS_SDRAM_1_MAXSIZE 0x40000000
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#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
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#define CONFIG_SRAM_BASE 0xd2800000
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/* Preserve the last 2 lwords for the boot-counter */
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#define CONFIG_SRAM_SIZE ((8 << 10) - 0x8)
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#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SRAM_BASE
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#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SRAM_SIZE
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#define CONFIG_SYS_INIT_SP_OFFSET \
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(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
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#define CONFIG_SYS_INIT_SP_ADDR \
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(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
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/*
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* SPL related defines
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*/
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#define CONFIG_SPL_TEXT_BASE 0xd2800b00
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#define CONFIG_SPL_MAX_SIZE (CONFIG_SRAM_SIZE - 0xb00)
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#define CONFIG_SPL_START_S_PATH "arch/arm/cpu/arm926ejs/spear"
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/*
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* Please select/define only one of the following
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* Each definition corresponds to a supported DDR chip.
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* DDR configuration is based on the following selection
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*/
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#define CONFIG_DDR_MT47H64M16 1
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#define CONFIG_DDR_MT47H32M16 0
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#define CONFIG_DDR_MT47H128M8 0
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/*
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* Synchronous/Asynchronous operation of DDR
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*
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* Select CONFIG_DDR_2HCLK for DDR clk = 333MHz, synchronous operation
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* Select CONFIG_DDR_HCLK for DDR clk = 166MHz, synchronous operation
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* Select CONFIG_DDR_PLL2 for DDR clk = PLL2, asynchronous operation
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*/
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#define CONFIG_DDR_2HCLK 1
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#define CONFIG_DDR_HCLK 0
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#define CONFIG_DDR_PLL2 0
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/*
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* xxx_BOOT_SUPPORTED macro defines whether a booting type is supported
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* or not. Modify/Add to only these macros to define new boot types
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*/
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#define USB_BOOT_SUPPORTED 0
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#define PCIE_BOOT_SUPPORTED 0
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#define SNOR_BOOT_SUPPORTED 1
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#define NAND_BOOT_SUPPORTED 1
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#define PNOR_BOOT_SUPPORTED 0
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#define TFTP_BOOT_SUPPORTED 0
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#define UART_BOOT_SUPPORTED 0
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#define SPI_BOOT_SUPPORTED 0
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#define I2C_BOOT_SUPPORTED 0
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#define MMC_BOOT_SUPPORTED 0
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#endif /* __CONFIG_H */
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