upstream u-boot with additional patches for our devices/boards: https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ; Gbit ethernet patch for some LIME2 revisions ; with SPI flash support
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u-boot/drivers/reset/stm32-reset.c

104 lines
2.5 KiB

/*
* Copyright (C) 2017, STMicroelectronics - All Rights Reserved
* Author(s): Patrice Chotard, <patrice.chotard@st.com> for STMicroelectronics.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <dm.h>
#include <errno.h>
#include <reset-uclass.h>
#include <asm/io.h>
/* reset clear offset for STM32MP RCC */
#define RCC_CL 0x4
enum rcc_type {
RCC_STM32 = 0,
RCC_STM32MP,
};
struct stm32_reset_priv {
fdt_addr_t base;
};
static int stm32_reset_request(struct reset_ctl *reset_ctl)
{
return 0;
}
static int stm32_reset_free(struct reset_ctl *reset_ctl)
{
return 0;
}
static int stm32_reset_assert(struct reset_ctl *reset_ctl)
{
struct stm32_reset_priv *priv = dev_get_priv(reset_ctl->dev);
int bank = (reset_ctl->id / BITS_PER_LONG) * 4;
int offset = reset_ctl->id % BITS_PER_LONG;
debug("%s: reset id = %ld bank = %d offset = %d)\n", __func__,
reset_ctl->id, bank, offset);
if (dev_get_driver_data(reset_ctl->dev) == RCC_STM32MP)
/* reset assert is done in rcc set register */
writel(BIT(offset), priv->base + bank);
else
setbits_le32(priv->base + bank, BIT(offset));
return 0;
}
static int stm32_reset_deassert(struct reset_ctl *reset_ctl)
{
struct stm32_reset_priv *priv = dev_get_priv(reset_ctl->dev);
int bank = (reset_ctl->id / BITS_PER_LONG) * 4;
int offset = reset_ctl->id % BITS_PER_LONG;
debug("%s: reset id = %ld bank = %d offset = %d)\n", __func__,
reset_ctl->id, bank, offset);
if (dev_get_driver_data(reset_ctl->dev) == RCC_STM32MP)
/* reset deassert is done in rcc clr register */
writel(BIT(offset), priv->base + bank + RCC_CL);
else
clrbits_le32(priv->base + bank, BIT(offset));
return 0;
}
static const struct reset_ops stm32_reset_ops = {
.request = stm32_reset_request,
.free = stm32_reset_free,
.rst_assert = stm32_reset_assert,
.rst_deassert = stm32_reset_deassert,
};
static int stm32_reset_probe(struct udevice *dev)
{
struct stm32_reset_priv *priv = dev_get_priv(dev);
priv->base = dev_read_addr(dev);
if (priv->base == FDT_ADDR_T_NONE) {
/* for MFD, get address of parent */
priv->base = dev_read_addr(dev->parent);
if (priv->base == FDT_ADDR_T_NONE)
return -EINVAL;
}
return 0;
}
static const struct udevice_id stm32_reset_ids[] = {
{ .compatible = "st,stm32mp1-rcc-rst", .data = RCC_STM32MP },
{ }
};
U_BOOT_DRIVER(stm32_rcc_reset) = {
.name = "stm32_rcc_reset",
.id = UCLASS_RESET,
.of_match = stm32_reset_ids,
.probe = stm32_reset_probe,
.priv_auto_alloc_size = sizeof(struct stm32_reset_priv),
.ops = &stm32_reset_ops,
};