upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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372 lines
9.2 KiB
372 lines
9.2 KiB
/*
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* Copyright 2008 Extreme Engineering Solutions, Inc.
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* Copyright 2007-2008 Freescale Semiconductor, Inc.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <pci.h>
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#include <asm/immap_85xx.h>
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#include <asm/fsl_pci.h>
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#include <libfdt.h>
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#include <fdt_support.h>
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int first_free_busno = 0;
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#ifdef CONFIG_PCI1
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static struct pci_controller pci1_hose;
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#endif
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#ifdef CONFIG_PCIE1
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static struct pci_controller pcie1_hose;
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#endif
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#ifdef CONFIG_PCIE2
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static struct pci_controller pcie2_hose;
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#endif
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#ifdef CONFIG_PCIE3
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static struct pci_controller pcie3_hose;
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#endif
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#ifdef CONFIG_MPC8572
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/* Correlate host/agent POR bits to usable info. Table 4-14 */
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struct host_agent_cfg_t {
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uchar pcie_root[3];
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uchar rio_host;
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} host_agent_cfg[8] = {
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{{0, 0, 0}, 0},
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{{0, 1, 1}, 1},
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{{1, 0, 1}, 0},
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{{1, 1, 0}, 1},
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{{0, 0, 1}, 0},
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{{0, 1, 0}, 1},
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{{1, 0, 0}, 0},
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{{1, 1, 1}, 1}
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};
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/* Correlate port width POR bits to usable info. Table 4-15 */
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struct io_port_cfg_t {
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uchar pcie_width[3];
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uchar rio_width;
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} io_port_cfg[16] = {
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{{0, 0, 0}, 0},
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{{0, 0, 0}, 0},
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{{4, 0, 0}, 0},
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{{4, 4, 0}, 0},
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{{0, 0, 0}, 0},
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{{0, 0, 0}, 0},
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{{0, 0, 0}, 4},
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{{4, 2, 2}, 0},
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{{0, 0, 0}, 0},
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{{0, 0, 0}, 0},
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{{0, 0, 0}, 0},
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{{4, 0, 0}, 4},
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{{4, 0, 0}, 4},
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{{0, 0, 0}, 4},
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{{0, 0, 0}, 4},
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{{8, 0, 0}, 0},
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};
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#elif defined CONFIG_MPC8548
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/* Correlate host/agent POR bits to usable info. Table 4-12 */
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struct host_agent_cfg_t {
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uchar pci_host[2];
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uchar pcie_root[1];
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uchar rio_host;
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} host_agent_cfg[8] = {
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{{1, 1}, {0}, 0},
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{{1, 1}, {1}, 0},
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{{1, 1}, {0}, 1},
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{{0, 0}, {0}, 0}, /* reserved */
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{{0, 1}, {1}, 0},
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{{1, 1}, {1}, 0},
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{{0, 1}, {1}, 1},
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{{1, 1}, {1}, 1}
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};
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/* Correlate port width POR bits to usable info. Table 4-13 */
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struct io_port_cfg_t {
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uchar pcie_width[1];
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uchar rio_width;
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} io_port_cfg[8] = {
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{{0}, 0},
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{{0}, 0},
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{{0}, 0},
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{{4}, 4},
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{{4}, 4},
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{{0}, 4},
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{{0}, 4},
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{{8}, 0},
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};
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#endif
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void pci_init_board(void)
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{
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struct pci_controller *hose;
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volatile ccsr_fsl_pci_t *pci;
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int width;
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int host;
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volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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uint devdisr = gur->devdisr;
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uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
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uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;
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struct pci_region *r;
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#ifdef CONFIG_PCI1
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uint pci_spd_norm = (gur->pordevsr & MPC85xx_PORDEVSR_PCI1_SPD);
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uint pci_32 = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32;
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uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB;
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uint pcix = gur->pordevsr & MPC85xx_PORDEVSR_PCI1;
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uint freq = CONFIG_SYS_CLK_FREQ / 1000 / 1000;
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width = 0; /* Silence compiler warning... */
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io_sel &= 0xf; /* Silence compiler warning... */
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pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR;
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hose = &pci1_hose;
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host = host_agent_cfg[host_agent].pci_host[0];
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r = hose->regions;
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if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
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printf("\n PCI1: %d bit %s, %s %d MHz, %s, %s\n",
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pci_32 ? 32 : 64,
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pcix ? "PCIX" : "PCI",
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pci_spd_norm ? ">=" : "<=",
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pcix ? freq * 2 : freq,
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host ? "host" : "agent",
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pci_arb ? "arbiter" : "external-arbiter");
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/* inbound */
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r += fsl_pci_setup_inbound_windows(r);
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/* outbound memory */
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pci_set_region(r++,
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CONFIG_SYS_PCI1_MEM_BASE,
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CONFIG_SYS_PCI1_MEM_PHYS,
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CONFIG_SYS_PCI1_MEM_SIZE,
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PCI_REGION_MEM);
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/* outbound io */
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pci_set_region(r++,
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CONFIG_SYS_PCI1_IO_BASE,
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CONFIG_SYS_PCI1_IO_PHYS,
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CONFIG_SYS_PCI1_IO_SIZE,
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PCI_REGION_IO);
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hose->region_count = r - hose->regions;
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hose->first_busno = first_free_busno;
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pci_setup_indirect(hose, (int)&pci->cfg_addr,
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(int)&pci->cfg_data);
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fsl_pci_init(hose);
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/* Unlock inbound PCI configuration cycles */
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if (!host)
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fsl_pci_config_unlock(hose);
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first_free_busno = hose->last_busno + 1;
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printf(" PCI1 on bus %02x - %02x\n",
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hose->first_busno, hose->last_busno);
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} else {
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printf(" PCI1: disabled\n");
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}
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#elif defined CONFIG_MPC8548
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/* PCI1 not present on MPC8572 */
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gur->devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */
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#endif
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#ifdef CONFIG_PCIE1
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pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR;
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hose = &pcie1_hose;
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host = host_agent_cfg[host_agent].pcie_root[0];
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width = io_port_cfg[io_sel].pcie_width[0];
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r = hose->regions;
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if (width && !(devdisr & MPC85xx_DEVDISR_PCIE)) {
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printf("\n PCIE1 connected as %s (x%d)",
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host ? "Root Complex" : "End Point", width);
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if (pci->pme_msg_det) {
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pci->pme_msg_det = 0xffffffff;
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debug(" with errors. Clearing. Now 0x%08x",
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pci->pme_msg_det);
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}
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printf("\n");
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/* inbound */
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r += fsl_pci_setup_inbound_windows(r);
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/* outbound memory */
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pci_set_region(r++,
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CONFIG_SYS_PCIE1_MEM_BASE,
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CONFIG_SYS_PCIE1_MEM_PHYS,
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CONFIG_SYS_PCIE1_MEM_SIZE,
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PCI_REGION_MEM);
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/* outbound io */
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pci_set_region(r++,
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CONFIG_SYS_PCIE1_IO_BASE,
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CONFIG_SYS_PCIE1_IO_PHYS,
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CONFIG_SYS_PCIE1_IO_SIZE,
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PCI_REGION_IO);
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hose->region_count = r - hose->regions;
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hose->first_busno = first_free_busno;
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pci_setup_indirect(hose, (int)&pci->cfg_addr,
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(int) &pci->cfg_data);
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fsl_pci_init(hose);
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/* Unlock inbound PCI configuration cycles */
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if (!host)
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fsl_pci_config_unlock(hose);
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first_free_busno = hose->last_busno + 1;
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printf(" PCIE1 on bus %02x - %02x\n",
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hose->first_busno, hose->last_busno);
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}
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#else
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gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */
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#endif /* CONFIG_PCIE1 */
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#ifdef CONFIG_PCIE2
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pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE2_ADDR;
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hose = &pcie2_hose;
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host = host_agent_cfg[host_agent].pcie_root[1];
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width = io_port_cfg[io_sel].pcie_width[1];
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r = hose->regions;
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if (width && !(devdisr & MPC85xx_DEVDISR_PCIE2)) {
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printf("\n PCIE2 connected as %s (x%d)",
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host ? "Root Complex" : "End Point", width);
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if (pci->pme_msg_det) {
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pci->pme_msg_det = 0xffffffff;
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debug(" with errors. Clearing. Now 0x%08x",
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pci->pme_msg_det);
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}
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printf("\n");
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/* inbound */
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r += fsl_pci_setup_inbound_windows(r);
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/* outbound memory */
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pci_set_region(r++,
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CONFIG_SYS_PCIE2_MEM_BASE,
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CONFIG_SYS_PCIE2_MEM_PHYS,
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CONFIG_SYS_PCIE2_MEM_SIZE,
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PCI_REGION_MEM);
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/* outbound io */
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pci_set_region(r++,
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CONFIG_SYS_PCIE2_IO_BASE,
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CONFIG_SYS_PCIE2_IO_PHYS,
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CONFIG_SYS_PCIE2_IO_SIZE,
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PCI_REGION_IO);
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hose->region_count = r - hose->regions;
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hose->first_busno = first_free_busno;
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pci_setup_indirect(hose, (int)&pci->cfg_addr,
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(int)&pci->cfg_data);
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fsl_pci_init(hose);
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/* Unlock inbound PCI configuration cycles */
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if (!host)
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fsl_pci_config_unlock(hose);
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first_free_busno = hose->last_busno + 1;
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printf(" PCIE2 on bus %02x - %02x\n",
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hose->first_busno, hose->last_busno);
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}
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#else
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gur->devdisr |= MPC85xx_DEVDISR_PCIE2; /* disable */
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#endif /* CONFIG_PCIE2 */
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#ifdef CONFIG_PCIE3
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pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE3_ADDR;
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hose = &pcie3_hose;
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host = host_agent_cfg[host_agent].pcie_root[2];
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width = io_port_cfg[io_sel].pcie_width[2];
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r = hose->regions;
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if (width && !(devdisr & MPC85xx_DEVDISR_PCIE3)) {
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printf("\n PCIE3 connected as %s (x%d)",
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host ? "Root Complex" : "End Point", width);
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if (pci->pme_msg_det) {
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pci->pme_msg_det = 0xffffffff;
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debug(" with errors. Clearing. Now 0x%08x",
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pci->pme_msg_det);
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}
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printf("\n");
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/* inbound */
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r += fsl_pci_setup_inbound_windows(r);
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/* outbound memory */
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pci_set_region(r++,
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CONFIG_SYS_PCIE3_MEM_BASE,
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CONFIG_SYS_PCIE3_MEM_PHYS,
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CONFIG_SYS_PCIE3_MEM_SIZE,
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PCI_REGION_MEM);
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/* outbound io */
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pci_set_region(r++,
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CONFIG_SYS_PCIE3_IO_BASE,
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CONFIG_SYS_PCIE3_IO_PHYS,
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CONFIG_SYS_PCIE3_IO_SIZE,
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PCI_REGION_IO);
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hose->region_count = r - hose->regions;
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hose->first_busno = first_free_busno;
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pci_setup_indirect(hose, (int)&pci->cfg_addr,
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(int)&pci->cfg_data);
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fsl_pci_init(hose);
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/* Unlock inbound PCI configuration cycles */
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if (!host)
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fsl_pci_config_unlock(hose);
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first_free_busno = hose->last_busno + 1;
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printf(" PCIE3 on bus %02x - %02x\n",
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hose->first_busno, hose->last_busno);
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}
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#else
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gur->devdisr |= MPC85xx_DEVDISR_PCIE3; /* disable */
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#endif /* CONFIG_PCIE3 */
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}
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#if defined(CONFIG_OF_BOARD_SETUP)
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void ft_board_pci_setup(void *blob, bd_t *bd)
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{
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/* TODO - make node name (eg pci0) dynamic */
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#ifdef CONFIG_PCI1
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ft_fsl_pci_setup(blob, "pci0", &pci1_hose);
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#endif
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#ifdef CONFIG_PCIE1
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ft_fsl_pci_setup(blob, "pci2", &pcie1_hose);
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#endif
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#ifdef CONFIG_PCIE2
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ft_fsl_pci_setup(blob, "pci1", &pcie2_hose);
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#endif
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#ifdef CONFIG_PCIE3
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ft_fsl_pci_setup(blob, "pci0", &pcie3_hose);
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#endif
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}
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#endif /* CONFIG_OF_BOARD_SETUP */
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