upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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552 lines
13 KiB
552 lines
13 KiB
/*
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* (C) Copyright 2003
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* Josef Baumgartner <josef.baumgartner@telex.de>
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*
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* MCF5282 additionals
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* (C) Copyright 2005
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* BuS Elektronik GmbH & Co. KG <esw@bus-elektronik.de>
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*
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* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
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* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
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* Hayden Fraser (Hayden.Fraser@freescale.com)
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <watchdog.h>
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#include <asm/immap.h>
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#if defined(CONFIG_M5253)
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/*
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* Breath some life into the CPU...
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*
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* Set up the memory map,
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* initialize a bunch of registers,
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* initialize the UPM's
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*/
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void cpu_init_f(void)
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{
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mbar_writeByte(MCFSIM_MPARK, 0x40); /* 5249 Internal Core takes priority over DMA */
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mbar_writeByte(MCFSIM_SYPCR, 0x00);
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mbar_writeByte(MCFSIM_SWIVR, 0x0f);
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mbar_writeByte(MCFSIM_SWSR, 0x00);
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mbar_writeByte(MCFSIM_SWDICR, 0x00);
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mbar_writeByte(MCFSIM_TIMER1ICR, 0x00);
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mbar_writeByte(MCFSIM_TIMER2ICR, 0x88);
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mbar_writeByte(MCFSIM_I2CICR, 0x00);
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mbar_writeByte(MCFSIM_UART1ICR, 0x00);
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mbar_writeByte(MCFSIM_UART2ICR, 0x00);
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mbar_writeByte(MCFSIM_ICR6, 0x00);
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mbar_writeByte(MCFSIM_ICR7, 0x00);
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mbar_writeByte(MCFSIM_ICR8, 0x00);
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mbar_writeByte(MCFSIM_ICR9, 0x00);
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mbar_writeByte(MCFSIM_QSPIICR, 0x00);
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mbar2_writeLong(MCFSIM_GPIO_INT_EN, 0x00000080);
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mbar2_writeByte(MCFSIM_INTBASE, 0x40); /* Base interrupts at 64 */
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mbar2_writeByte(MCFSIM_SPURVEC, 0x00);
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/*mbar2_writeLong(MCFSIM_IDECONFIG1, 0x00000020); */ /* Enable a 1 cycle pre-drive cycle on CS1 */
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/*
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* Setup chip selects...
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*/
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mbar_writeShort(MCFSIM_CSAR1, CFG_CSAR1);
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mbar_writeShort(MCFSIM_CSCR1, CFG_CSCR1);
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mbar_writeLong(MCFSIM_CSMR1, CFG_CSMR1);
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mbar_writeShort(MCFSIM_CSAR0, CFG_CSAR0);
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mbar_writeShort(MCFSIM_CSCR0, CFG_CSCR0);
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mbar_writeLong(MCFSIM_CSMR0, CFG_CSMR0);
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/* enable instruction cache now */
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icache_enable();
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}
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/*initialize higher level parts of CPU like timers */
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int cpu_init_r(void)
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{
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return (0);
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}
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void uart_port_conf(void)
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{
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/* Setup Ports: */
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switch (CFG_UART_PORT) {
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case 0:
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break;
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case 1:
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break;
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case 2:
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break;
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}
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}
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#endif /* #if defined(CONFIG_M5253) */
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#if defined(CONFIG_M5271)
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void cpu_init_f(void)
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{
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#ifndef CONFIG_WATCHDOG
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/* Disable the watchdog if we aren't using it */
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mbar_writeShort(MCF_WTM_WCR, 0);
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#endif
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/* Set clockspeed to 100MHz */
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mbar_writeShort(MCF_FMPLL_SYNCR,
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MCF_FMPLL_SYNCR_MFD(0) | MCF_FMPLL_SYNCR_RFD(0));
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while (!mbar_readByte(MCF_FMPLL_SYNSR) & MCF_FMPLL_SYNSR_LOCK) ;
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}
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/*
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* initialize higher level parts of CPU like timers
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*/
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int cpu_init_r(void)
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{
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return (0);
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}
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void uart_port_conf(void)
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{
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/* Setup Ports: */
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switch (CFG_UART_PORT) {
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case 0:
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mbar_writeShort(MCF_GPIO_PAR_UART, MCF_GPIO_PAR_UART_U0TXD |
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MCF_GPIO_PAR_UART_U0RXD);
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break;
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case 1:
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mbar_writeShort(MCF_GPIO_PAR_UART,
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MCF_GPIO_PAR_UART_U1RXD_UART1 |
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MCF_GPIO_PAR_UART_U1TXD_UART1);
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break;
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case 2:
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mbar_writeShort(MCF_GPIO_PAR_UART, 0x3000);
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break;
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}
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}
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#endif
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#if defined(CONFIG_M5272)
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/*
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* Breath some life into the CPU...
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*
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* Set up the memory map,
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* initialize a bunch of registers,
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* initialize the UPM's
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*/
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void cpu_init_f(void)
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{
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/* if we come from RAM we assume the CPU is
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* already initialized.
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*/
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#ifndef CONFIG_MONITOR_IS_IN_RAM
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volatile sysctrl_t *sysctrl = (sysctrl_t *) (CFG_MBAR);
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volatile gpio_t *gpio = (gpio_t *) (MMAP_GPIO);
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volatile csctrl_t *csctrl = (csctrl_t *) (MMAP_FBCS);
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sysctrl->sc_scr = CFG_SCR;
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sysctrl->sc_spr = CFG_SPR;
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/* Setup Ports: */
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gpio->gpio_pacnt = CFG_PACNT;
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gpio->gpio_paddr = CFG_PADDR;
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gpio->gpio_padat = CFG_PADAT;
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gpio->gpio_pbcnt = CFG_PBCNT;
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gpio->gpio_pbddr = CFG_PBDDR;
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gpio->gpio_pbdat = CFG_PBDAT;
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gpio->gpio_pdcnt = CFG_PDCNT;
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/* Memory Controller: */
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csctrl->cs_br0 = CFG_BR0_PRELIM;
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csctrl->cs_or0 = CFG_OR0_PRELIM;
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#if (defined(CFG_OR1_PRELIM) && defined(CFG_BR1_PRELIM))
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csctrl->cs_br1 = CFG_BR1_PRELIM;
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csctrl->cs_or1 = CFG_OR1_PRELIM;
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#endif
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#if defined(CFG_OR2_PRELIM) && defined(CFG_BR2_PRELIM)
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csctrl->cs_br2 = CFG_BR2_PRELIM;
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csctrl->cs_or2 = CFG_OR2_PRELIM;
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#endif
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#if defined(CFG_OR3_PRELIM) && defined(CFG_BR3_PRELIM)
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csctrl->cs_br3 = CFG_BR3_PRELIM;
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csctrl->cs_or3 = CFG_OR3_PRELIM;
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#endif
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#if defined(CFG_OR4_PRELIM) && defined(CFG_BR4_PRELIM)
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csctrl->cs_br4 = CFG_BR4_PRELIM;
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csctrl->cs_or4 = CFG_OR4_PRELIM;
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#endif
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#if defined(CFG_OR5_PRELIM) && defined(CFG_BR5_PRELIM)
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csctrl->cs_br5 = CFG_BR5_PRELIM;
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csctrl->cs_or5 = CFG_OR5_PRELIM;
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#endif
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#if defined(CFG_OR6_PRELIM) && defined(CFG_BR6_PRELIM)
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csctrl->cs_br6 = CFG_BR6_PRELIM;
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csctrl->cs_or6 = CFG_OR6_PRELIM;
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#endif
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#if defined(CFG_OR7_PRELIM) && defined(CFG_BR7_PRELIM)
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csctrl->cs_br7 = CFG_BR7_PRELIM;
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csctrl->cs_or7 = CFG_OR7_PRELIM;
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#endif
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#endif /* #ifndef CONFIG_MONITOR_IS_IN_RAM */
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/* enable instruction cache now */
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icache_enable();
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}
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/*
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* initialize higher level parts of CPU like timers
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*/
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int cpu_init_r(void)
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{
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return (0);
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}
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void uart_port_conf(void)
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{
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volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
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/* Setup Ports: */
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switch (CFG_UART_PORT) {
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case 0:
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gpio->gpio_pbcnt &= ~(GPIO_PBCNT_PB0MSK | GPIO_PBCNT_PB1MSK);
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gpio->gpio_pbcnt |= (GPIO_PBCNT_URT0_TXD | GPIO_PBCNT_URT0_RXD);
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break;
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case 1:
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gpio->gpio_pdcnt &= ~(GPIO_PDCNT_PD1MSK | GPIO_PDCNT_PD4MSK);
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gpio->gpio_pdcnt |= (GPIO_PDCNT_URT1_RXD | GPIO_PDCNT_URT1_TXD);
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break;
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}
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}
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#endif /* #if defined(CONFIG_M5272) */
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#if defined(CONFIG_M5282)
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/*
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* Breath some life into the CPU...
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*
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* Set up the memory map,
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* initialize a bunch of registers,
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* initialize the UPM's
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*/
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void cpu_init_f(void)
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{
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#ifndef CONFIG_WATCHDOG
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/* disable watchdog if we aren't using it */
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MCFWTM_WCR = 0;
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#endif
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#ifndef CONFIG_MONITOR_IS_IN_RAM
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/* Set speed /PLL */
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MCFCLOCK_SYNCR =
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MCFCLOCK_SYNCR_MFD(CFG_MFD) | MCFCLOCK_SYNCR_RFD(CFG_RFD);
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while (!(MCFCLOCK_SYNSR & MCFCLOCK_SYNSR_LOCK)) ;
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MCFGPIO_PBCDPAR = 0xc0;
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/* Set up the GPIO ports */
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#ifdef CFG_PEPAR
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MCFGPIO_PEPAR = CFG_PEPAR;
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#endif
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#ifdef CFG_PFPAR
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MCFGPIO_PFPAR = CFG_PFPAR;
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#endif
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#ifdef CFG_PJPAR
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MCFGPIO_PJPAR = CFG_PJPAR;
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#endif
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#ifdef CFG_PSDPAR
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MCFGPIO_PSDPAR = CFG_PSDPAR;
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#endif
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#ifdef CFG_PASPAR
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MCFGPIO_PASPAR = CFG_PASPAR;
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#endif
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#ifdef CFG_PEHLPAR
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MCFGPIO_PEHLPAR = CFG_PEHLPAR;
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#endif
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#ifdef CFG_PQSPAR
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MCFGPIO_PQSPAR = CFG_PQSPAR;
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#endif
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#ifdef CFG_PTCPAR
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MCFGPIO_PTCPAR = CFG_PTCPAR;
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#endif
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#ifdef CFG_PTDPAR
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MCFGPIO_PTDPAR = CFG_PTDPAR;
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#endif
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#ifdef CFG_PUAPAR
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MCFGPIO_PUAPAR = CFG_PUAPAR;
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#endif
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#ifdef CFG_DDRUA
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MCFGPIO_DDRUA = CFG_DDRUA;
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#endif
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/* This is probably a bad place to setup chip selects, but everyone
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else is doing it! */
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#if defined(CFG_CS0_BASE) & defined(CFG_CS0_SIZE) & \
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defined(CFG_CS0_WIDTH) & defined(CFG_CS0_RO) & \
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defined(CFG_CS0_WS)
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MCFCSM_CSAR0 = (CFG_CS0_BASE >> 16) & 0xFFFF;
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#if (CFG_CS0_WIDTH == 8)
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#define CFG_CS0_PS MCFCSM_CSCR_PS_8
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#elif (CFG_CS0_WIDTH == 16)
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#define CFG_CS0_PS MCFCSM_CSCR_PS_16
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#elif (CFG_CS0_WIDTH == 32)
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#define CFG_CS0_PS MCFCSM_CSCR_PS_32
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#else
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#error "CFG_CS0_WIDTH: Fault - wrong bus with for CS0"
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#endif
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MCFCSM_CSCR0 = MCFCSM_CSCR_WS(CFG_CS0_WS)
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| CFG_CS0_PS | MCFCSM_CSCR_AA;
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#if (CFG_CS0_RO != 0)
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MCFCSM_CSMR0 = MCFCSM_CSMR_BAM(CFG_CS0_SIZE - 1)
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| MCFCSM_CSMR_WP | MCFCSM_CSMR_V;
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#else
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MCFCSM_CSMR0 = MCFCSM_CSMR_BAM(CFG_CS0_SIZE - 1) | MCFCSM_CSMR_V;
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#endif
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#else
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#waring "Chip Select 0 are not initialized/used"
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#endif
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#if defined(CFG_CS1_BASE) & defined(CFG_CS1_SIZE) & \
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defined(CFG_CS1_WIDTH) & defined(CFG_CS1_RO) & \
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defined(CFG_CS1_WS)
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MCFCSM_CSAR1 = (CFG_CS1_BASE >> 16) & 0xFFFF;
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#if (CFG_CS1_WIDTH == 8)
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#define CFG_CS1_PS MCFCSM_CSCR_PS_8
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#elif (CFG_CS1_WIDTH == 16)
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#define CFG_CS1_PS MCFCSM_CSCR_PS_16
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#elif (CFG_CS1_WIDTH == 32)
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#define CFG_CS1_PS MCFCSM_CSCR_PS_32
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#else
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#error "CFG_CS1_WIDTH: Fault - wrong bus with for CS1"
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#endif
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MCFCSM_CSCR1 = MCFCSM_CSCR_WS(CFG_CS1_WS)
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| CFG_CS1_PS | MCFCSM_CSCR_AA;
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#if (CFG_CS1_RO != 0)
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MCFCSM_CSMR1 = MCFCSM_CSMR_BAM(CFG_CS1_SIZE - 1)
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| MCFCSM_CSMR_WP | MCFCSM_CSMR_V;
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#else
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MCFCSM_CSMR1 = MCFCSM_CSMR_BAM(CFG_CS1_SIZE - 1)
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| MCFCSM_CSMR_V;
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#endif
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#else
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#warning "Chip Select 1 are not initialized/used"
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#endif
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#if defined(CFG_CS2_BASE) & defined(CFG_CS2_SIZE) & \
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defined(CFG_CS2_WIDTH) & defined(CFG_CS2_RO) & \
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defined(CFG_CS2_WS)
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MCFCSM_CSAR2 = (CFG_CS2_BASE >> 16) & 0xFFFF;
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#if (CFG_CS2_WIDTH == 8)
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#define CFG_CS2_PS MCFCSM_CSCR_PS_8
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#elif (CFG_CS2_WIDTH == 16)
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#define CFG_CS2_PS MCFCSM_CSCR_PS_16
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#elif (CFG_CS2_WIDTH == 32)
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#define CFG_CS2_PS MCFCSM_CSCR_PS_32
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#else
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#error "CFG_CS2_WIDTH: Fault - wrong bus with for CS2"
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#endif
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MCFCSM_CSCR2 = MCFCSM_CSCR_WS(CFG_CS2_WS)
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| CFG_CS2_PS | MCFCSM_CSCR_AA;
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#if (CFG_CS2_RO != 0)
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MCFCSM_CSMR2 = MCFCSM_CSMR_BAM(CFG_CS2_SIZE - 1)
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| MCFCSM_CSMR_WP | MCFCSM_CSMR_V;
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#else
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MCFCSM_CSMR2 = MCFCSM_CSMR_BAM(CFG_CS2_SIZE - 1)
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| MCFCSM_CSMR_V;
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#endif
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#else
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#warning "Chip Select 2 are not initialized/used"
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#endif
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#if defined(CFG_CS3_BASE) & defined(CFG_CS3_SIZE) & \
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defined(CFG_CS3_WIDTH) & defined(CFG_CS3_RO) & \
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defined(CFG_CS3_WS)
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MCFCSM_CSAR3 = (CFG_CS3_BASE >> 16) & 0xFFFF;
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#if (CFG_CS3_WIDTH == 8)
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#define CFG_CS3_PS MCFCSM_CSCR_PS_8
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#elif (CFG_CS3_WIDTH == 16)
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#define CFG_CS3_PS MCFCSM_CSCR_PS_16
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#elif (CFG_CS3_WIDTH == 32)
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#define CFG_CS3_PS MCFCSM_CSCR_PS_32
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#else
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#error "CFG_CS3_WIDTH: Fault - wrong bus with for CS1"
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#endif
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MCFCSM_CSCR3 = MCFCSM_CSCR_WS(CFG_CS3_WS)
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| CFG_CS3_PS | MCFCSM_CSCR_AA;
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#if (CFG_CS3_RO != 0)
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MCFCSM_CSMR3 = MCFCSM_CSMR_BAM(CFG_CS3_SIZE - 1)
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| MCFCSM_CSMR_WP | MCFCSM_CSMR_V;
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#else
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MCFCSM_CSMR3 = MCFCSM_CSMR_BAM(CFG_CS3_SIZE - 1)
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| MCFCSM_CSMR_V;
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#endif
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#else
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#warning "Chip Select 3 are not initialized/used"
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#endif
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#endif /* CONFIG_MONITOR_IS_IN_RAM */
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/* defer enabling cache until boot (see do_go) */
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/* icache_enable(); */
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}
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/*
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* initialize higher level parts of CPU like timers
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*/
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int cpu_init_r(void)
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{
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return (0);
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}
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void uart_port_conf(void)
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{
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/* Setup Ports: */
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switch (CFG_UART_PORT) {
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case 0:
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MCFGPIO_PUAPAR &= 0xFc;
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MCFGPIO_PUAPAR |= 0x03;
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break;
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case 1:
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MCFGPIO_PUAPAR &= 0xF3;
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MCFGPIO_PUAPAR |= 0x0C;
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break;
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case 2:
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MCFGPIO_PASPAR &= 0xFF0F;
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MCFGPIO_PASPAR |= 0x00A0;
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break;
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}
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}
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#endif
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#if defined(CONFIG_M5249)
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/*
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|
* Breath some life into the CPU...
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|
*
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|
* Set up the memory map,
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|
* initialize a bunch of registers,
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|
* initialize the UPM's
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|
*/
|
|
void cpu_init_f(void)
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|
{
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/*
|
|
* NOTE: by setting the GPIO_FUNCTION registers, we ensure that the UART pins
|
|
* (UART0: gpio 30,27, UART1: gpio 31, 28) will be used as UART pins
|
|
* which is their primary function.
|
|
* ~Jeremy
|
|
*/
|
|
mbar2_writeLong(MCFSIM_GPIO_FUNC, CFG_GPIO_FUNC);
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mbar2_writeLong(MCFSIM_GPIO1_FUNC, CFG_GPIO1_FUNC);
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mbar2_writeLong(MCFSIM_GPIO_EN, CFG_GPIO_EN);
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|
mbar2_writeLong(MCFSIM_GPIO1_EN, CFG_GPIO1_EN);
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mbar2_writeLong(MCFSIM_GPIO_OUT, CFG_GPIO_OUT);
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|
mbar2_writeLong(MCFSIM_GPIO1_OUT, CFG_GPIO1_OUT);
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|
|
|
/*
|
|
* dBug Compliance:
|
|
* You can verify these values by using dBug's 'ird'
|
|
* (Internal Register Display) command
|
|
* ~Jeremy
|
|
*
|
|
*/
|
|
mbar_writeByte(MCFSIM_MPARK, 0x30); /* 5249 Internal Core takes priority over DMA */
|
|
mbar_writeByte(MCFSIM_SYPCR, 0x00);
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|
mbar_writeByte(MCFSIM_SWIVR, 0x0f);
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|
mbar_writeByte(MCFSIM_SWSR, 0x00);
|
|
mbar_writeLong(MCFSIM_IMR, 0xfffffbff);
|
|
mbar_writeByte(MCFSIM_SWDICR, 0x00);
|
|
mbar_writeByte(MCFSIM_TIMER1ICR, 0x00);
|
|
mbar_writeByte(MCFSIM_TIMER2ICR, 0x88);
|
|
mbar_writeByte(MCFSIM_I2CICR, 0x00);
|
|
mbar_writeByte(MCFSIM_UART1ICR, 0x00);
|
|
mbar_writeByte(MCFSIM_UART2ICR, 0x00);
|
|
mbar_writeByte(MCFSIM_ICR6, 0x00);
|
|
mbar_writeByte(MCFSIM_ICR7, 0x00);
|
|
mbar_writeByte(MCFSIM_ICR8, 0x00);
|
|
mbar_writeByte(MCFSIM_ICR9, 0x00);
|
|
mbar_writeByte(MCFSIM_QSPIICR, 0x00);
|
|
|
|
mbar2_writeLong(MCFSIM_GPIO_INT_EN, 0x00000080);
|
|
mbar2_writeByte(MCFSIM_INTBASE, 0x40); /* Base interrupts at 64 */
|
|
mbar2_writeByte(MCFSIM_SPURVEC, 0x00);
|
|
mbar2_writeLong(MCFSIM_IDECONFIG1, 0x00000020); /* Enable a 1 cycle pre-drive cycle on CS1 */
|
|
|
|
/* Setup interrupt priorities for gpio7 */
|
|
/* mbar2_writeLong(MCFSIM_INTLEV5, 0x70000000); */
|
|
|
|
/* IDE Config registers */
|
|
mbar2_writeLong(MCFSIM_IDECONFIG1, 0x00000020);
|
|
mbar2_writeLong(MCFSIM_IDECONFIG2, 0x00000000);
|
|
|
|
/*
|
|
* Setup chip selects...
|
|
*/
|
|
|
|
mbar_writeShort(MCFSIM_CSAR1, CFG_CSAR1);
|
|
mbar_writeShort(MCFSIM_CSCR1, CFG_CSCR1);
|
|
mbar_writeLong(MCFSIM_CSMR1, CFG_CSMR1);
|
|
|
|
mbar_writeShort(MCFSIM_CSAR0, CFG_CSAR0);
|
|
mbar_writeShort(MCFSIM_CSCR0, CFG_CSCR0);
|
|
mbar_writeLong(MCFSIM_CSMR0, CFG_CSMR0);
|
|
|
|
/* enable instruction cache now */
|
|
icache_enable();
|
|
}
|
|
|
|
/*
|
|
* initialize higher level parts of CPU like timers
|
|
*/
|
|
int cpu_init_r(void)
|
|
{
|
|
return (0);
|
|
}
|
|
|
|
void uart_port_conf(void)
|
|
{
|
|
/* Setup Ports: */
|
|
switch (CFG_UART_PORT) {
|
|
case 0:
|
|
break;
|
|
case 1:
|
|
break;
|
|
}
|
|
}
|
|
#endif /* #if defined(CONFIG_M5249) */
|
|
|