upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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396 lines
11 KiB
396 lines
11 KiB
/******************************************************************
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* Copyright 2008 Mentor Graphics Corporation
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* Copyright (C) 2008 by Texas Instruments
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*
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* This file is part of the Inventra Controller Driver for Linux.
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*
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* The Inventra Controller Driver for Linux is free software; you
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* can redistribute it and/or modify it under the terms of the GNU
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* General Public License version 2 as published by the Free Software
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* Foundation.
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*
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* The Inventra Controller Driver for Linux is distributed in
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* the hope that it will be useful, but WITHOUT ANY WARRANTY;
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* without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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* License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with The Inventra Controller Driver for Linux ; if not,
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* write to the Free Software Foundation, Inc., 59 Temple Place,
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* Suite 330, Boston, MA 02111-1307 USA
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*
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* ANY DOWNLOAD, USE, REPRODUCTION, MODIFICATION OR DISTRIBUTION
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* OF THIS DRIVER INDICATES YOUR COMPLETE AND UNCONDITIONAL ACCEPTANCE
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* OF THOSE TERMS.THIS DRIVER IS PROVIDED "AS IS" AND MENTOR GRAPHICS
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* MAKES NO WARRANTIES, EXPRESS OR IMPLIED, RELATED TO THIS DRIVER.
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* MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES
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* OF MERCHANTABILITY; FITNESS FOR A PARTICULAR PURPOSE AND
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* NON-INFRINGEMENT. MENTOR GRAPHICS DOES NOT PROVIDE SUPPORT
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* SERVICES OR UPDATES FOR THIS DRIVER, EVEN IF YOU ARE A MENTOR
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* GRAPHICS SUPPORT CUSTOMER.
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******************************************************************/
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#ifndef __MUSB_HDRC_DEFS_H__
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#define __MUSB_HDRC_DEFS_H__
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#include <usb.h>
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#include <usb_defs.h>
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#include <asm/io.h>
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#ifdef CONFIG_USB_BLACKFIN
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# include "blackfin_usb.h"
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#endif
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#define MUSB_EP0_FIFOSIZE 64 /* This is non-configurable */
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/* EP0 */
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struct musb_ep0_regs {
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u16 reserved4;
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u16 csr0;
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u16 reserved5;
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u16 reserved6;
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u16 count0;
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u8 host_type0;
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u8 host_naklimit0;
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u8 reserved7;
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u8 reserved8;
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u8 reserved9;
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u8 configdata;
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};
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/* EP 1-15 */
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struct musb_epN_regs {
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u16 txmaxp;
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u16 txcsr;
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u16 rxmaxp;
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u16 rxcsr;
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u16 rxcount;
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u8 txtype;
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u8 txinterval;
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u8 rxtype;
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u8 rxinterval;
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u8 reserved0;
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u8 fifosize;
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};
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/* Mentor USB core register overlay structure */
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#ifndef musb_regs
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struct musb_regs {
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/* common registers */
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u8 faddr;
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u8 power;
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u16 intrtx;
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u16 intrrx;
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u16 intrtxe;
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u16 intrrxe;
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u8 intrusb;
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u8 intrusbe;
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u16 frame;
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u8 index;
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u8 testmode;
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/* indexed registers */
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u16 txmaxp;
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u16 txcsr;
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u16 rxmaxp;
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u16 rxcsr;
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u16 rxcount;
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u8 txtype;
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u8 txinterval;
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u8 rxtype;
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u8 rxinterval;
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u8 reserved0;
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u8 fifosize;
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/* fifo */
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u32 fifox[16];
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/* OTG, dynamic FIFO, version & vendor registers */
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u8 devctl;
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u8 reserved1;
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u8 txfifosz;
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u8 rxfifosz;
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u16 txfifoadd;
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u16 rxfifoadd;
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u32 vcontrol;
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u16 hwvers;
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u16 reserved2a[1];
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u8 ulpi_busctl;
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u8 reserved2b[1];
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u16 reserved2[3];
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u8 epinfo;
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u8 raminfo;
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u8 linkinfo;
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u8 vplen;
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u8 hseof1;
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u8 fseof1;
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u8 lseof1;
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u8 reserved3;
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/* target address registers */
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struct musb_tar_regs {
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u8 txfuncaddr;
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u8 reserved0;
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u8 txhubaddr;
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u8 txhubport;
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u8 rxfuncaddr;
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u8 reserved1;
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u8 rxhubaddr;
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u8 rxhubport;
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} tar[16];
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/*
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* endpoint registers
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* ep0 elements are valid when array index is 0
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* otherwise epN is valid
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*/
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union musb_ep_regs {
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struct musb_ep0_regs ep0;
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struct musb_epN_regs epN;
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} ep[16];
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} __attribute__((packed, aligned(32)));
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#endif
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/*
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* MUSB Register bits
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*/
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/* POWER */
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#define MUSB_POWER_ISOUPDATE 0x80
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#define MUSB_POWER_SOFTCONN 0x40
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#define MUSB_POWER_HSENAB 0x20
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#define MUSB_POWER_HSMODE 0x10
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#define MUSB_POWER_RESET 0x08
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#define MUSB_POWER_RESUME 0x04
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#define MUSB_POWER_SUSPENDM 0x02
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#define MUSB_POWER_ENSUSPEND 0x01
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#define MUSB_POWER_HSMODE_SHIFT 4
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/* INTRUSB */
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#define MUSB_INTR_SUSPEND 0x01
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#define MUSB_INTR_RESUME 0x02
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#define MUSB_INTR_RESET 0x04
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#define MUSB_INTR_BABBLE 0x04
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#define MUSB_INTR_SOF 0x08
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#define MUSB_INTR_CONNECT 0x10
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#define MUSB_INTR_DISCONNECT 0x20
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#define MUSB_INTR_SESSREQ 0x40
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#define MUSB_INTR_VBUSERROR 0x80 /* For SESSION end */
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/* DEVCTL */
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#define MUSB_DEVCTL_BDEVICE 0x80
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#define MUSB_DEVCTL_FSDEV 0x40
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#define MUSB_DEVCTL_LSDEV 0x20
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#define MUSB_DEVCTL_VBUS 0x18
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#define MUSB_DEVCTL_VBUS_SHIFT 3
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#define MUSB_DEVCTL_HM 0x04
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#define MUSB_DEVCTL_HR 0x02
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#define MUSB_DEVCTL_SESSION 0x01
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/* ULPI VBUSCONTROL */
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#define ULPI_USE_EXTVBUS 0x01
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#define ULPI_USE_EXTVBUSIND 0x02
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/* TESTMODE */
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#define MUSB_TEST_FORCE_HOST 0x80
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#define MUSB_TEST_FIFO_ACCESS 0x40
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#define MUSB_TEST_FORCE_FS 0x20
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#define MUSB_TEST_FORCE_HS 0x10
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#define MUSB_TEST_PACKET 0x08
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#define MUSB_TEST_K 0x04
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#define MUSB_TEST_J 0x02
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#define MUSB_TEST_SE0_NAK 0x01
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/* Allocate for double-packet buffering (effectively doubles assigned _SIZE) */
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#define MUSB_FIFOSZ_DPB 0x10
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/* Allocation size (8, 16, 32, ... 4096) */
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#define MUSB_FIFOSZ_SIZE 0x0f
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/* CSR0 */
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#define MUSB_CSR0_FLUSHFIFO 0x0100
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#define MUSB_CSR0_TXPKTRDY 0x0002
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#define MUSB_CSR0_RXPKTRDY 0x0001
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/* CSR0 in Peripheral mode */
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#define MUSB_CSR0_P_SVDSETUPEND 0x0080
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#define MUSB_CSR0_P_SVDRXPKTRDY 0x0040
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#define MUSB_CSR0_P_SENDSTALL 0x0020
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#define MUSB_CSR0_P_SETUPEND 0x0010
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#define MUSB_CSR0_P_DATAEND 0x0008
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#define MUSB_CSR0_P_SENTSTALL 0x0004
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/* CSR0 in Host mode */
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#define MUSB_CSR0_H_DIS_PING 0x0800
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#define MUSB_CSR0_H_WR_DATATOGGLE 0x0400 /* Set to allow setting: */
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#define MUSB_CSR0_H_DATATOGGLE 0x0200 /* Data toggle control */
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#define MUSB_CSR0_H_NAKTIMEOUT 0x0080
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#define MUSB_CSR0_H_STATUSPKT 0x0040
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#define MUSB_CSR0_H_REQPKT 0x0020
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#define MUSB_CSR0_H_ERROR 0x0010
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#define MUSB_CSR0_H_SETUPPKT 0x0008
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#define MUSB_CSR0_H_RXSTALL 0x0004
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/* CSR0 bits to avoid zeroing (write zero clears, write 1 ignored) */
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#define MUSB_CSR0_P_WZC_BITS \
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(MUSB_CSR0_P_SENTSTALL)
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#define MUSB_CSR0_H_WZC_BITS \
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(MUSB_CSR0_H_NAKTIMEOUT | MUSB_CSR0_H_RXSTALL \
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| MUSB_CSR0_RXPKTRDY)
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/* TxType/RxType */
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#define MUSB_TYPE_SPEED 0xc0
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#define MUSB_TYPE_SPEED_SHIFT 6
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#define MUSB_TYPE_SPEED_HIGH 1
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#define MUSB_TYPE_SPEED_FULL 2
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#define MUSB_TYPE_SPEED_LOW 3
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#define MUSB_TYPE_PROTO 0x30 /* Implicitly zero for ep0 */
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#define MUSB_TYPE_PROTO_SHIFT 4
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#define MUSB_TYPE_REMOTE_END 0xf /* Implicitly zero for ep0 */
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#define MUSB_TYPE_PROTO_BULK 2
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#define MUSB_TYPE_PROTO_INTR 3
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/* CONFIGDATA */
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#define MUSB_CONFIGDATA_MPRXE 0x80 /* Auto bulk pkt combining */
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#define MUSB_CONFIGDATA_MPTXE 0x40 /* Auto bulk pkt splitting */
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#define MUSB_CONFIGDATA_BIGENDIAN 0x20
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#define MUSB_CONFIGDATA_HBRXE 0x10 /* HB-ISO for RX */
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#define MUSB_CONFIGDATA_HBTXE 0x08 /* HB-ISO for TX */
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#define MUSB_CONFIGDATA_DYNFIFO 0x04 /* Dynamic FIFO sizing */
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#define MUSB_CONFIGDATA_SOFTCONE 0x02 /* SoftConnect */
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#define MUSB_CONFIGDATA_UTMIDW 0x01 /* Data width 0/1 => 8/16bits */
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/* TXCSR in Peripheral and Host mode */
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#define MUSB_TXCSR_AUTOSET 0x8000
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#define MUSB_TXCSR_MODE 0x2000
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#define MUSB_TXCSR_DMAENAB 0x1000
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#define MUSB_TXCSR_FRCDATATOG 0x0800
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#define MUSB_TXCSR_DMAMODE 0x0400
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#define MUSB_TXCSR_CLRDATATOG 0x0040
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#define MUSB_TXCSR_FLUSHFIFO 0x0008
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#define MUSB_TXCSR_FIFONOTEMPTY 0x0002
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#define MUSB_TXCSR_TXPKTRDY 0x0001
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/* TXCSR in Peripheral mode */
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#define MUSB_TXCSR_P_ISO 0x4000
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#define MUSB_TXCSR_P_INCOMPTX 0x0080
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#define MUSB_TXCSR_P_SENTSTALL 0x0020
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#define MUSB_TXCSR_P_SENDSTALL 0x0010
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#define MUSB_TXCSR_P_UNDERRUN 0x0004
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/* TXCSR in Host mode */
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#define MUSB_TXCSR_H_WR_DATATOGGLE 0x0200
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#define MUSB_TXCSR_H_DATATOGGLE 0x0100
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#define MUSB_TXCSR_H_NAKTIMEOUT 0x0080
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#define MUSB_TXCSR_H_RXSTALL 0x0020
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#define MUSB_TXCSR_H_ERROR 0x0004
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#define MUSB_TXCSR_H_DATATOGGLE_SHIFT 8
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/* TXCSR bits to avoid zeroing (write zero clears, write 1 ignored) */
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#define MUSB_TXCSR_P_WZC_BITS \
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(MUSB_TXCSR_P_INCOMPTX | MUSB_TXCSR_P_SENTSTALL \
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| MUSB_TXCSR_P_UNDERRUN | MUSB_TXCSR_FIFONOTEMPTY)
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#define MUSB_TXCSR_H_WZC_BITS \
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(MUSB_TXCSR_H_NAKTIMEOUT | MUSB_TXCSR_H_RXSTALL \
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| MUSB_TXCSR_H_ERROR | MUSB_TXCSR_FIFONOTEMPTY)
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/* RXCSR in Peripheral and Host mode */
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#define MUSB_RXCSR_AUTOCLEAR 0x8000
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#define MUSB_RXCSR_DMAENAB 0x2000
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#define MUSB_RXCSR_DISNYET 0x1000
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#define MUSB_RXCSR_PID_ERR 0x1000
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#define MUSB_RXCSR_DMAMODE 0x0800
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#define MUSB_RXCSR_INCOMPRX 0x0100
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#define MUSB_RXCSR_CLRDATATOG 0x0080
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#define MUSB_RXCSR_FLUSHFIFO 0x0010
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#define MUSB_RXCSR_DATAERROR 0x0008
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#define MUSB_RXCSR_FIFOFULL 0x0002
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#define MUSB_RXCSR_RXPKTRDY 0x0001
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/* RXCSR in Peripheral mode */
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#define MUSB_RXCSR_P_ISO 0x4000
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#define MUSB_RXCSR_P_SENTSTALL 0x0040
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#define MUSB_RXCSR_P_SENDSTALL 0x0020
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#define MUSB_RXCSR_P_OVERRUN 0x0004
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/* RXCSR in Host mode */
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#define MUSB_RXCSR_H_AUTOREQ 0x4000
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#define MUSB_RXCSR_H_WR_DATATOGGLE 0x0400
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#define MUSB_RXCSR_H_DATATOGGLE 0x0200
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#define MUSB_RXCSR_H_RXSTALL 0x0040
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#define MUSB_RXCSR_H_REQPKT 0x0020
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#define MUSB_RXCSR_H_ERROR 0x0004
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#define MUSB_S_RXCSR_H_DATATOGGLE 9
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/* RXCSR bits to avoid zeroing (write zero clears, write 1 ignored) */
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#define MUSB_RXCSR_P_WZC_BITS \
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(MUSB_RXCSR_P_SENTSTALL | MUSB_RXCSR_P_OVERRUN \
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| MUSB_RXCSR_RXPKTRDY)
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#define MUSB_RXCSR_H_WZC_BITS \
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(MUSB_RXCSR_H_RXSTALL | MUSB_RXCSR_H_ERROR \
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| MUSB_RXCSR_DATAERROR | MUSB_RXCSR_RXPKTRDY)
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/* HUBADDR */
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#define MUSB_HUBADDR_MULTI_TT 0x80
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/* Endpoint configuration information. Note: The value of endpoint fifo size
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* element should be either 8,16,32,64,128,256,512,1024,2048 or 4096. Other
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* values are not supported
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*/
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struct musb_epinfo {
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u8 epnum; /* endpoint number */
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u8 epdir; /* endpoint direction */
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u16 epsize; /* endpoint FIFO size */
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};
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/*
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* Platform specific MUSB configuration. Any platform using the musb
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* functionality should create one instance of this structure in the
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* platform specific file.
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*/
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struct musb_config {
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struct musb_regs *regs;
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u32 timeout;
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u8 musb_speed;
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u8 extvbus;
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};
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/* externally defined data */
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extern struct musb_config musb_cfg;
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extern struct musb_regs *musbr;
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/* exported functions */
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extern void musb_start(void);
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extern void musb_configure_ep(const struct musb_epinfo *epinfo, u8 cnt);
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extern void write_fifo(u8 ep, u32 length, void *fifo_data);
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extern void read_fifo(u8 ep, u32 length, void *fifo_data);
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#if defined(CONFIG_USB_BLACKFIN)
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/* Every USB register is accessed as a 16-bit even if the value itself
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* is only 8-bits in size. Fun stuff.
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*/
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# undef readb
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# define readb(addr) (u8)bfin_read16(addr)
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# undef writeb
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# define writeb(b, addr) bfin_write16(addr, b)
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# undef MUSB_TXCSR_MODE /* not supported */
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# define MUSB_TXCSR_MODE 0
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/*
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* The USB PHY on current Blackfin processors is a UTMI+ level 2 PHY.
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* However, it has no ULPI support - so there are no registers at all.
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* That means accesses to ULPI_BUSCONTROL have to be abstracted away.
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*/
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static inline u8 musb_read_ulpi_buscontrol(struct musb_regs *musbr)
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{
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return 0;
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}
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static inline void musb_write_ulpi_buscontrol(struct musb_regs *musbr, u8 val)
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{}
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#else
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static inline u8 musb_read_ulpi_buscontrol(struct musb_regs *musbr)
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{
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return readb(&musbr->ulpi_busctl);
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}
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static inline void musb_write_ulpi_buscontrol(struct musb_regs *musbr, u8 val)
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{
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writeb(val, &musbr->ulpi_busctl);
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}
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#endif
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#endif /* __MUSB_HDRC_DEFS_H__ */
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