upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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320 lines
9.4 KiB
320 lines
9.4 KiB
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2007-2008 Freescale Semiconductor, Inc.
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* Dave Liu <daveliu@freescale.com>
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*/
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#ifndef __FSL_SATA_H__
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#define __FSL_SATA_H__
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#define SATA_HC_MAX_NUM 4 /* Max host controller numbers */
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#define SATA_HC_MAX_CMD 16 /* Max command queue depth per host controller */
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#define SATA_HC_MAX_PORT 16 /* Max port number per host controller */
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/*
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* SATA Host Controller Registers
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*/
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typedef struct fsl_sata_reg {
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/* SATA command registers */
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u32 cqr; /* Command queue register */
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u8 res1[0x4];
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u32 car; /* Command active register */
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u8 res2[0x4];
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u32 ccr; /* Command completed register */
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u8 res3[0x4];
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u32 cer; /* Command error register */
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u8 res4[0x4];
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u32 der; /* Device error register */
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u32 chba; /* Command header base address */
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u32 hstatus; /* Host status register */
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u32 hcontrol; /* Host control register */
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u32 cqpmp; /* Port number queue register */
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u32 sig; /* Signature register */
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u32 icc; /* Interrupt coalescing control register */
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u8 res5[0xc4];
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/* SATA supperset registers */
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u32 sstatus; /* SATA interface status register */
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u32 serror; /* SATA interface error register */
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u32 scontrol; /* SATA interface control register */
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u32 snotification; /* SATA interface notification register */
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u8 res6[0x30];
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/* SATA control status registers */
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u32 transcfg; /* Transport layer configuration */
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u32 transstatus; /* Transport layer status */
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u32 linkcfg; /* Link layer configuration */
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u32 linkcfg1; /* Link layer configuration1 */
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u32 linkcfg2; /* Link layer configuration2 */
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u32 linkstatus; /* Link layer status */
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u32 linkstatus1; /* Link layer status1 */
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u32 phyctrlcfg; /* PHY control configuration */
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u8 res7[0x2b0];
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/* SATA system control registers */
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u32 syspr; /* System priority register - big endian */
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u8 res8[0xbec];
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} __attribute__ ((packed)) fsl_sata_reg_t;
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/* HStatus register
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*/
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#define HSTATUS_ONOFF 0x80000000 /* Online/offline status */
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#define HSTATUS_FORCE_OFFLINE 0x40000000 /* In process going offline */
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#define HSTATUS_BIST_ERR 0x20000000
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/* Fatal error */
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#define HSTATUS_MASTER_ERR 0x00004000
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#define HSTATUS_DATA_UNDERRUN 0x00002000
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#define HSTATUS_DATA_OVERRUN 0x00001000
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#define HSTATUS_CRC_ERR_TX 0x00000800
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#define HSTATUS_CRC_ERR_RX 0x00000400
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#define HSTATUS_FIFO_OVERFLOW_TX 0x00000200
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#define HSTATUS_FIFO_OVERFLOW_RX 0x00000100
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#define HSTATUS_FATAL_ERR_ALL (HSTATUS_MASTER_ERR | \
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HSTATUS_DATA_UNDERRUN | \
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HSTATUS_DATA_OVERRUN | \
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HSTATUS_CRC_ERR_TX | \
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HSTATUS_CRC_ERR_RX | \
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HSTATUS_FIFO_OVERFLOW_TX | \
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HSTATUS_FIFO_OVERFLOW_RX)
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/* Interrupt status */
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#define HSTATUS_FATAL_ERR 0x00000020
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#define HSTATUS_PHY_RDY 0x00000010
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#define HSTATUS_SIGNATURE 0x00000008
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#define HSTATUS_SNOTIFY 0x00000004
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#define HSTATUS_DEVICE_ERR 0x00000002
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#define HSTATUS_CMD_COMPLETE 0x00000001
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/* HControl register
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*/
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#define HCONTROL_ONOFF 0x80000000 /* Online or offline request */
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#define HCONTROL_FORCE_OFFLINE 0x40000000 /* Force offline request */
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#define HCONTROL_ENTERPRISE_EN 0x10000000 /* Enterprise mode enabled */
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#define HCONTROL_HDR_SNOOP 0x00000400 /* Command header snoop */
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#define HCONTROL_PMP_ATTACHED 0x00000200 /* Port multiplier attached */
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/* Interrupt enable */
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#define HCONTROL_FATAL_ERR 0x00000020
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#define HCONTROL_PHY_RDY 0x00000010
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#define HCONTROL_SIGNATURE 0x00000008
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#define HCONTROL_SNOTIFY 0x00000004
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#define HCONTROL_DEVICE_ERR 0x00000002
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#define HCONTROL_CMD_COMPLETE 0x00000001
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#define HCONTROL_INT_EN_ALL (HCONTROL_FATAL_ERR | \
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HCONTROL_PHY_RDY | \
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HCONTROL_SIGNATURE | \
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HCONTROL_SNOTIFY | \
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HCONTROL_DEVICE_ERR | \
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HCONTROL_CMD_COMPLETE)
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/* SStatus register
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*/
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#define SSTATUS_IPM_MASK 0x00000780
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#define SSTATUS_IPM_NOPRESENT 0x00000000
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#define SSTATUS_IPM_ACTIVE 0x00000080
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#define SSTATUS_IPM_PATIAL 0x00000100
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#define SSTATUS_IPM_SLUMBER 0x00000300
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#define SSTATUS_SPD_MASK 0x000000f0
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#define SSTATUS_SPD_GEN1 0x00000010
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#define SSTATUS_SPD_GEN2 0x00000020
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#define SSTATUS_DET_MASK 0x0000000f
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#define SSTATUS_DET_NODEVICE 0x00000000
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#define SSTATUS_DET_DISCONNECT 0x00000001
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#define SSTATUS_DET_CONNECT 0x00000003
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#define SSTATUS_DET_PHY_OFFLINE 0x00000004
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/* SControl register
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*/
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#define SCONTROL_SPM_MASK 0x0000f000
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#define SCONTROL_SPM_GO_PARTIAL 0x00001000
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#define SCONTROL_SPM_GO_SLUMBER 0x00002000
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#define SCONTROL_SPM_GO_ACTIVE 0x00004000
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#define SCONTROL_IPM_MASK 0x00000f00
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#define SCONTROL_IPM_NO_RESTRICT 0x00000000
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#define SCONTROL_IPM_PARTIAL 0x00000100
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#define SCONTROL_IPM_SLUMBER 0x00000200
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#define SCONTROL_IPM_PART_SLUM 0x00000300
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#define SCONTROL_SPD_MASK 0x000000f0
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#define SCONTROL_SPD_NO_RESTRICT 0x00000000
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#define SCONTROL_SPD_GEN1 0x00000010
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#define SCONTROL_SPD_GEN2 0x00000020
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#define SCONTROL_DET_MASK 0x0000000f
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#define SCONTROL_DET_HRESET 0x00000001
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#define SCONTROL_DET_DISABLE 0x00000004
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/* TransCfg register
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*/
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#define TRANSCFG_DFIS_SIZE_SHIFT 16
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#define TRANSCFG_RX_WATER_MARK_MASK 0x0000001f
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/* PhyCtrlCfg register
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*/
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#define PHYCTRLCFG_FPRFTI_MASK 0x00000018
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#define PHYCTRLCFG_LOOPBACK_MASK 0x0000000e
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/*
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* Command Header Entry
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*/
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typedef struct cmd_hdr_entry {
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__le32 cda; /* Command Descriptor Address,
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4 bytes aligned */
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__le32 prde_fis_len; /* Number of PRD entries and FIS length */
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__le32 ttl; /* Total transfer length */
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__le32 attribute; /* the attribute of command */
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} __attribute__ ((packed)) cmd_hdr_entry_t;
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#define SATA_HC_CMD_HDR_ENTRY_SIZE sizeof(struct cmd_hdr_entry)
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/* cda
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*/
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#define CMD_HDR_CDA_ALIGN 4
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/* prde_fis_len
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*/
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#define CMD_HDR_PRD_ENTRY_SHIFT 16
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#define CMD_HDR_PRD_ENTRY_MASK 0x003f0000
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#define CMD_HDR_FIS_LEN_SHIFT 2
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/* attribute
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*/
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#define CMD_HDR_ATTR_RES 0x00000800 /* Reserved bit, should be 1 */
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#define CMD_HDR_ATTR_VBIST 0x00000400 /* Vendor BIST */
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#define CMD_HDR_ATTR_SNOOP 0x00000200 /* Snoop enable for all descriptor */
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#define CMD_HDR_ATTR_FPDMA 0x00000100 /* FPDMA queued command */
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#define CMD_HDR_ATTR_RESET 0x00000080 /* Reset - a SRST or device reset */
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#define CMD_HDR_ATTR_BIST 0x00000040 /* BIST - require the host to enter BIST mode */
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#define CMD_HDR_ATTR_ATAPI 0x00000020 /* ATAPI command */
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#define CMD_HDR_ATTR_TAG 0x0000001f /* TAG mask */
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/* command type
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*/
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enum cmd_type {
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CMD_VENDOR_BIST,
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CMD_BIST,
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CMD_RESET, /* SRST or device reset */
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CMD_ATAPI,
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CMD_NCQ,
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CMD_ATA, /* None of all above */
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};
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/*
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* Command Header Table
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*/
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typedef struct cmd_hdr_tbl {
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cmd_hdr_entry_t cmd_slot[SATA_HC_MAX_CMD];
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} __attribute__ ((packed)) cmd_hdr_tbl_t;
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#define SATA_HC_CMD_HDR_TBL_SIZE sizeof(struct cmd_hdr_tbl)
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#define SATA_HC_CMD_HDR_TBL_ALIGN 4
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/*
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* PRD entry - Physical Region Descriptor entry
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*/
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typedef struct prd_entry {
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__le32 dba; /* Data base address, 4 bytes aligned */
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u32 res1;
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u32 res2;
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__le32 ext_c_ddc; /* Indirect PRD flags, snoop and data word count */
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} __attribute__ ((packed)) prd_entry_t;
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#define SATA_HC_CMD_DESC_PRD_SIZE sizeof(struct prd_entry)
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/* dba
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*/
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#define PRD_ENTRY_DBA_ALIGN 4
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/* ext_c_ddc
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*/
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#define PRD_ENTRY_EXT 0x80000000 /* extension flag */
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#ifdef CONFIG_FSL_SATA_V2
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#define PRD_ENTRY_DATA_SNOOP 0x10000000 /* Data snoop enable */
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#else
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#define PRD_ENTRY_DATA_SNOOP 0x00400000 /* Data snoop enable */
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#endif
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#define PRD_ENTRY_LEN_MASK 0x003fffff /* Data word count */
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#define PRD_ENTRY_MAX_XFER_SZ (PRD_ENTRY_LEN_MASK + 1)
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/*
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* This SATA host controller supports a max of 16 direct PRD entries, but if use
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* chained indirect PRD entries, then the contollers supports upto a max of 63
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* entries including direct and indirect PRD entries.
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* The PRDT is an array of 63 PRD entries contigiously, but the PRD entries#15
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* will be setup as an indirect descriptor, pointing to it's next (contigious)
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* PRD entries#16.
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*/
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#define SATA_HC_MAX_PRD 63 /* Max PRD entry numbers per command */
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#define SATA_HC_MAX_PRD_DIRECT 16 /* Direct PRDT entries */
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#define SATA_HC_MAX_PRD_USABLE (SATA_HC_MAX_PRD - 1)
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#define SATA_HC_MAX_XFER_LEN 0x4000000
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/*
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* PRDT - Physical Region Descriptor Table
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*/
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typedef struct prdt {
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prd_entry_t prdt[SATA_HC_MAX_PRD];
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} __attribute__ ((packed)) prdt_t;
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/*
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* Command Descriptor
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*/
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#define SATA_HC_CMD_DESC_CFIS_SIZE 32 /* bytes */
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#define SATA_HC_CMD_DESC_SFIS_SIZE 32 /* bytes */
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#define SATA_HC_CMD_DESC_ACMD_SIZE 16 /* bytes */
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#define SATA_HC_CMD_DESC_RES 16 /* bytes */
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typedef struct cmd_desc {
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u8 cfis[SATA_HC_CMD_DESC_CFIS_SIZE];
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u8 sfis[SATA_HC_CMD_DESC_SFIS_SIZE];
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u8 acmd[SATA_HC_CMD_DESC_ACMD_SIZE];
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u8 res[SATA_HC_CMD_DESC_RES];
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prd_entry_t prdt[SATA_HC_MAX_PRD];
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} __attribute__ ((packed)) cmd_desc_t;
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#define SATA_HC_CMD_DESC_SIZE sizeof(struct cmd_desc)
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#define SATA_HC_CMD_DESC_ALIGN 4
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/*
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* SATA device driver info
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*/
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typedef struct fsl_sata_info {
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u32 sata_reg_base;
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u32 flags;
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} fsl_sata_info_t;
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#define FLAGS_DMA 0x00000000
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#define FLAGS_FPDMA 0x00000001
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/*
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* SATA device driver struct
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*/
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typedef struct fsl_sata {
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char name[12];
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fsl_sata_reg_t *reg_base; /* the base address of controller register */
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void *cmd_hdr_tbl_offset; /* alloc address of command header table */
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cmd_hdr_tbl_t *cmd_hdr; /* aligned address of command header table */
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void *cmd_desc_offset; /* alloc address of command descriptor */
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cmd_desc_t *cmd_desc; /* aligned address of command descriptor */
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int link; /* PHY link status */
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/* device attribute */
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int ata_device_type; /* device type */
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int lba48;
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int queue_depth; /* Max NCQ queue depth */
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u16 pio;
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u16 mwdma;
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u16 udma;
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int wcache;
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int flush;
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int flush_ext;
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} fsl_sata_t;
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#define READ_CMD 0
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#define WRITE_CMD 1
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#endif /* __FSL_SATA_H__ */
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