upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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428 lines
10 KiB
428 lines
10 KiB
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (c) 2012 The Chromium OS Authors.
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*
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* TSC calibration codes are adapted from Linux kernel
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* arch/x86/kernel/tsc_msr.c and arch/x86/kernel/tsc.c
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*/
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#include <common.h>
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#include <dm.h>
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#include <malloc.h>
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#include <timer.h>
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#include <asm/cpu.h>
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#include <asm/io.h>
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#include <asm/i8254.h>
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#include <asm/ibmpc.h>
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#include <asm/msr.h>
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#include <asm/u-boot-x86.h>
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#define MAX_NUM_FREQS 9
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DECLARE_GLOBAL_DATA_PTR;
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static unsigned long cpu_mhz_from_cpuid(void)
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{
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if (gd->arch.x86_vendor != X86_VENDOR_INTEL)
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return 0;
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if (cpuid_eax(0) < 0x16)
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return 0;
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return cpuid_eax(0x16);
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}
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/*
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* According to Intel 64 and IA-32 System Programming Guide,
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* if MSR_PERF_STAT[31] is set, the maximum resolved bus ratio can be
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* read in MSR_PLATFORM_ID[12:8], otherwise in MSR_PERF_STAT[44:40].
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* Unfortunately some Intel Atom SoCs aren't quite compliant to this,
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* so we need manually differentiate SoC families. This is what the
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* field msr_plat does.
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*/
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struct freq_desc {
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u8 x86_family; /* CPU family */
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u8 x86_model; /* model */
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/* 2: use 100MHz, 1: use MSR_PLATFORM_INFO, 0: MSR_IA32_PERF_STATUS */
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u8 msr_plat;
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u32 freqs[MAX_NUM_FREQS];
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};
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static struct freq_desc freq_desc_tables[] = {
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/* PNW */
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{ 6, 0x27, 0, { 0, 0, 0, 0, 0, 99840, 0, 83200, 0 } },
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/* CLV+ */
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{ 6, 0x35, 0, { 0, 133200, 0, 0, 0, 99840, 0, 83200, 0 } },
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/* TNG - Intel Atom processor Z3400 series */
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{ 6, 0x4a, 1, { 0, 100000, 133300, 0, 0, 0, 0, 0, 0 } },
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/* VLV2 - Intel Atom processor E3000, Z3600, Z3700 series */
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{ 6, 0x37, 1, { 83300, 100000, 133300, 116700, 80000, 0, 0, 0, 0 } },
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/* ANN - Intel Atom processor Z3500 series */
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{ 6, 0x5a, 1, { 83300, 100000, 133300, 100000, 0, 0, 0, 0, 0 } },
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/* AMT - Intel Atom processor X7-Z8000 and X5-Z8000 series */
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{ 6, 0x4c, 1, { 83300, 100000, 133300, 116700,
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80000, 93300, 90000, 88900, 87500 } },
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/* Ivybridge */
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{ 6, 0x3a, 2, { 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
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};
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static int match_cpu(u8 family, u8 model)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(freq_desc_tables); i++) {
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if ((family == freq_desc_tables[i].x86_family) &&
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(model == freq_desc_tables[i].x86_model))
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return i;
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}
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return -1;
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}
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/* Map CPU reference clock freq ID(0-7) to CPU reference clock freq(KHz) */
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#define id_to_freq(cpu_index, freq_id) \
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(freq_desc_tables[cpu_index].freqs[freq_id])
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/*
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* TSC on Intel Atom SoCs capable of determining TSC frequency by MSR is
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* reliable and the frequency is known (provided by HW).
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*
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* On these platforms PIT/HPET is generally not available so calibration won't
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* work at all and there is no other clocksource to act as a watchdog for the
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* TSC, so we have no other choice than to trust it.
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*
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* Returns the TSC frequency in MHz or 0 if HW does not provide it.
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*/
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static unsigned long __maybe_unused cpu_mhz_from_msr(void)
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{
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u32 lo, hi, ratio, freq_id, freq;
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unsigned long res;
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int cpu_index;
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if (gd->arch.x86_vendor != X86_VENDOR_INTEL)
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return 0;
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cpu_index = match_cpu(gd->arch.x86, gd->arch.x86_model);
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if (cpu_index < 0)
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return 0;
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if (freq_desc_tables[cpu_index].msr_plat) {
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rdmsr(MSR_PLATFORM_INFO, lo, hi);
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ratio = (lo >> 8) & 0xff;
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} else {
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rdmsr(MSR_IA32_PERF_STATUS, lo, hi);
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ratio = (hi >> 8) & 0x1f;
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}
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debug("Maximum core-clock to bus-clock ratio: 0x%x\n", ratio);
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if (freq_desc_tables[cpu_index].msr_plat == 2) {
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/* TODO: Figure out how best to deal with this */
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freq = 100000;
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debug("Using frequency: %u KHz\n", freq);
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} else {
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/* Get FSB FREQ ID */
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rdmsr(MSR_FSB_FREQ, lo, hi);
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freq_id = lo & 0x7;
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freq = id_to_freq(cpu_index, freq_id);
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debug("Resolved frequency ID: %u, frequency: %u KHz\n",
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freq_id, freq);
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}
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/* TSC frequency = maximum resolved freq * maximum resolved bus ratio */
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res = freq * ratio / 1000;
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debug("TSC runs at %lu MHz\n", res);
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return res;
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}
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/*
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* This reads the current MSB of the PIT counter, and
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* checks if we are running on sufficiently fast and
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* non-virtualized hardware.
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*
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* Our expectations are:
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*
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* - the PIT is running at roughly 1.19MHz
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*
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* - each IO is going to take about 1us on real hardware,
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* but we allow it to be much faster (by a factor of 10) or
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* _slightly_ slower (ie we allow up to a 2us read+counter
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* update - anything else implies a unacceptably slow CPU
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* or PIT for the fast calibration to work.
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*
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* - with 256 PIT ticks to read the value, we have 214us to
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* see the same MSB (and overhead like doing a single TSC
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* read per MSB value etc).
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*
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* - We're doing 2 reads per loop (LSB, MSB), and we expect
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* them each to take about a microsecond on real hardware.
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* So we expect a count value of around 100. But we'll be
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* generous, and accept anything over 50.
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*
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* - if the PIT is stuck, and we see *many* more reads, we
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* return early (and the next caller of pit_expect_msb()
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* then consider it a failure when they don't see the
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* next expected value).
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*
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* These expectations mean that we know that we have seen the
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* transition from one expected value to another with a fairly
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* high accuracy, and we didn't miss any events. We can thus
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* use the TSC value at the transitions to calculate a pretty
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* good value for the TSC frequencty.
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*/
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static inline int pit_verify_msb(unsigned char val)
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{
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/* Ignore LSB */
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inb(0x42);
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return inb(0x42) == val;
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}
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static inline int pit_expect_msb(unsigned char val, u64 *tscp,
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unsigned long *deltap)
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{
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int count;
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u64 tsc = 0, prev_tsc = 0;
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for (count = 0; count < 50000; count++) {
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if (!pit_verify_msb(val))
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break;
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prev_tsc = tsc;
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tsc = rdtsc();
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}
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*deltap = rdtsc() - prev_tsc;
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*tscp = tsc;
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/*
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* We require _some_ success, but the quality control
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* will be based on the error terms on the TSC values.
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*/
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return count > 5;
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}
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/*
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* How many MSB values do we want to see? We aim for
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* a maximum error rate of 500ppm (in practice the
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* real error is much smaller), but refuse to spend
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* more than 50ms on it.
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*/
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#define MAX_QUICK_PIT_MS 50
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#define MAX_QUICK_PIT_ITERATIONS (MAX_QUICK_PIT_MS * PIT_TICK_RATE / 1000 / 256)
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static unsigned long __maybe_unused quick_pit_calibrate(void)
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{
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int i;
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u64 tsc, delta;
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unsigned long d1, d2;
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/* Set the Gate high, disable speaker */
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outb((inb(0x61) & ~0x02) | 0x01, 0x61);
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/*
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* Counter 2, mode 0 (one-shot), binary count
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*
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* NOTE! Mode 2 decrements by two (and then the
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* output is flipped each time, giving the same
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* final output frequency as a decrement-by-one),
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* so mode 0 is much better when looking at the
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* individual counts.
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*/
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outb(0xb0, 0x43);
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/* Start at 0xffff */
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outb(0xff, 0x42);
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outb(0xff, 0x42);
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/*
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* The PIT starts counting at the next edge, so we
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* need to delay for a microsecond. The easiest way
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* to do that is to just read back the 16-bit counter
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* once from the PIT.
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*/
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pit_verify_msb(0);
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if (pit_expect_msb(0xff, &tsc, &d1)) {
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for (i = 1; i <= MAX_QUICK_PIT_ITERATIONS; i++) {
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if (!pit_expect_msb(0xff-i, &delta, &d2))
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break;
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/*
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* Iterate until the error is less than 500 ppm
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*/
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delta -= tsc;
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if (d1+d2 >= delta >> 11)
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continue;
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/*
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* Check the PIT one more time to verify that
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* all TSC reads were stable wrt the PIT.
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*
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* This also guarantees serialization of the
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* last cycle read ('d2') in pit_expect_msb.
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*/
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if (!pit_verify_msb(0xfe - i))
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break;
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goto success;
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}
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}
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debug("Fast TSC calibration failed\n");
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return 0;
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success:
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/*
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* Ok, if we get here, then we've seen the
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* MSB of the PIT decrement 'i' times, and the
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* error has shrunk to less than 500 ppm.
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*
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* As a result, we can depend on there not being
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* any odd delays anywhere, and the TSC reads are
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* reliable (within the error).
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*
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* kHz = ticks / time-in-seconds / 1000;
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* kHz = (t2 - t1) / (I * 256 / PIT_TICK_RATE) / 1000
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* kHz = ((t2 - t1) * PIT_TICK_RATE) / (I * 256 * 1000)
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*/
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delta *= PIT_TICK_RATE;
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delta /= (i*256*1000);
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debug("Fast TSC calibration using PIT\n");
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return delta / 1000;
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}
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/* Get the speed of the TSC timer in MHz */
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unsigned notrace long get_tbclk_mhz(void)
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{
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return get_tbclk() / 1000000;
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}
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static ulong get_ms_timer(void)
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{
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return (get_ticks() * 1000) / get_tbclk();
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}
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ulong get_timer(ulong base)
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{
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return get_ms_timer() - base;
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}
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ulong notrace timer_get_us(void)
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{
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return get_ticks() / get_tbclk_mhz();
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}
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ulong timer_get_boot_us(void)
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{
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return timer_get_us();
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}
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void __udelay(unsigned long usec)
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{
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u64 now = get_ticks();
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u64 stop;
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stop = now + usec * get_tbclk_mhz();
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while ((int64_t)(stop - get_ticks()) > 0)
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#if defined(CONFIG_QEMU) && defined(CONFIG_SMP)
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/*
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* Add a 'pause' instruction on qemu target,
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* to give other VCPUs a chance to run.
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*/
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asm volatile("pause");
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#else
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;
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#endif
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}
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static int tsc_timer_get_count(struct udevice *dev, u64 *count)
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{
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u64 now_tick = rdtsc();
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*count = now_tick - gd->arch.tsc_base;
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return 0;
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}
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static void tsc_timer_ensure_setup(bool stop)
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{
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if (gd->arch.tsc_base)
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return;
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gd->arch.tsc_base = rdtsc();
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if (!gd->arch.clock_rate) {
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unsigned long fast_calibrate;
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fast_calibrate = cpu_mhz_from_cpuid();
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if (fast_calibrate)
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goto done;
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fast_calibrate = cpu_mhz_from_msr();
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if (fast_calibrate)
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goto done;
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fast_calibrate = quick_pit_calibrate();
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if (fast_calibrate)
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goto done;
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if (stop)
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panic("TSC frequency is ZERO");
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else
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return;
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done:
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gd->arch.clock_rate = fast_calibrate * 1000000;
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}
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}
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static int tsc_timer_probe(struct udevice *dev)
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{
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struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev);
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/* Try hardware calibration first */
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tsc_timer_ensure_setup(false);
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if (!gd->arch.clock_rate) {
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/*
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* Use the clock frequency specified in the
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* device tree as last resort
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*/
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if (!uc_priv->clock_rate)
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panic("TSC frequency is ZERO");
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} else {
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uc_priv->clock_rate = gd->arch.clock_rate;
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}
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return 0;
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}
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unsigned long notrace timer_early_get_rate(void)
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{
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/*
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* When TSC timer is used as the early timer, be warned that the timer
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* clock rate can only be calibrated via some hardware ways. Specifying
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* it in the device tree won't work for the early timer.
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*/
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tsc_timer_ensure_setup(true);
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return gd->arch.clock_rate;
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}
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u64 notrace timer_early_get_count(void)
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{
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return rdtsc() - gd->arch.tsc_base;
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}
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static const struct timer_ops tsc_timer_ops = {
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.get_count = tsc_timer_get_count,
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};
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static const struct udevice_id tsc_timer_ids[] = {
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{ .compatible = "x86,tsc-timer", },
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{ }
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};
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U_BOOT_DRIVER(tsc_timer) = {
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.name = "tsc_timer",
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.id = UCLASS_TIMER,
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.of_match = tsc_timer_ids,
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.probe = tsc_timer_probe,
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.ops = &tsc_timer_ops,
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.flags = DM_FLAG_PRE_RELOC,
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};
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