upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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73 lines
1.6 KiB
73 lines
1.6 KiB
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2013 Altera Corporation <www.altera.com>
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*/
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#include <common.h>
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#include <watchdog.h>
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#include <asm/io.h>
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#include <asm/utils.h>
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#define DW_WDT_CR 0x00
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#define DW_WDT_TORR 0x04
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#define DW_WDT_CRR 0x0C
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#define DW_WDT_CR_EN_OFFSET 0x00
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#define DW_WDT_CR_RMOD_OFFSET 0x01
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#define DW_WDT_CR_RMOD_VAL 0x00
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#define DW_WDT_CRR_RESTART_VAL 0x76
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/*
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* Set the watchdog time interval.
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* Counter is 32 bit.
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*/
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static int designware_wdt_settimeout(unsigned int timeout)
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{
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signed int i;
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/* calculate the timeout range value */
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i = (log_2_n_round_up(timeout * CONFIG_DW_WDT_CLOCK_KHZ)) - 16;
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if (i > 15)
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i = 15;
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if (i < 0)
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i = 0;
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writel((i | (i << 4)), (CONFIG_DW_WDT_BASE + DW_WDT_TORR));
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return 0;
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}
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static void designware_wdt_enable(void)
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{
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writel(((DW_WDT_CR_RMOD_VAL << DW_WDT_CR_RMOD_OFFSET) |
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(0x1 << DW_WDT_CR_EN_OFFSET)),
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(CONFIG_DW_WDT_BASE + DW_WDT_CR));
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}
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static unsigned int designware_wdt_is_enabled(void)
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{
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unsigned long val;
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val = readl((CONFIG_DW_WDT_BASE + DW_WDT_CR));
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return val & 0x1;
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}
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#if defined(CONFIG_HW_WATCHDOG)
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void hw_watchdog_reset(void)
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{
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if (designware_wdt_is_enabled())
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/* restart the watchdog counter */
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writel(DW_WDT_CRR_RESTART_VAL,
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(CONFIG_DW_WDT_BASE + DW_WDT_CRR));
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}
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void hw_watchdog_init(void)
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{
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/* reset to disable the watchdog */
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hw_watchdog_reset();
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/* set timer in miliseconds */
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designware_wdt_settimeout(CONFIG_WATCHDOG_TIMEOUT_MSECS);
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/* enable the watchdog */
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designware_wdt_enable();
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/* reset the watchdog */
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hw_watchdog_reset();
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}
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#endif
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