upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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127 lines
2.9 KiB
127 lines
2.9 KiB
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Xilinx AXI platforms watchdog timer driver.
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*
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* Author(s): Michal Simek <michal.simek@xilinx.com>
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* Shreenidhi Shedi <yesshedi@gmail.com>
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*
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* Copyright (c) 2011-2018 Xilinx Inc.
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*/
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#include <common.h>
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#include <dm.h>
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#include <wdt.h>
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#include <linux/io.h>
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#define XWT_CSR0_WRS_MASK 0x00000008 /* Reset status Mask */
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#define XWT_CSR0_WDS_MASK 0x00000004 /* Timer state Mask */
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#define XWT_CSR0_EWDT1_MASK 0x00000002 /* Enable bit 1 Mask*/
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#define XWT_CSRX_EWDT2_MASK 0x00000001 /* Enable bit 2 Mask */
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struct watchdog_regs {
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u32 twcsr0; /* 0x0 */
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u32 twcsr1; /* 0x4 */
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u32 tbr; /* 0x8 */
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};
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struct xlnx_wdt_platdata {
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bool enable_once;
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struct watchdog_regs *regs;
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};
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static int xlnx_wdt_reset(struct udevice *dev)
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{
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u32 reg;
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struct xlnx_wdt_platdata *platdata = dev_get_platdata(dev);
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debug("%s ", __func__);
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/* Read the current contents of TCSR0 */
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reg = readl(&platdata->regs->twcsr0);
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/* Clear the watchdog WDS bit */
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if (reg & (XWT_CSR0_EWDT1_MASK | XWT_CSRX_EWDT2_MASK))
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writel(reg | XWT_CSR0_WDS_MASK, &platdata->regs->twcsr0);
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return 0;
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}
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static int xlnx_wdt_stop(struct udevice *dev)
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{
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u32 reg;
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struct xlnx_wdt_platdata *platdata = dev_get_platdata(dev);
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if (platdata->enable_once) {
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debug("Can't stop Xilinx watchdog.\n");
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return -EBUSY;
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}
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/* Read the current contents of TCSR0 */
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reg = readl(&platdata->regs->twcsr0);
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writel(reg & ~XWT_CSR0_EWDT1_MASK, &platdata->regs->twcsr0);
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writel(~XWT_CSRX_EWDT2_MASK, &platdata->regs->twcsr1);
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debug("Watchdog disabled!\n");
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return 0;
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}
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static int xlnx_wdt_start(struct udevice *dev, u64 timeout, ulong flags)
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{
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struct xlnx_wdt_platdata *platdata = dev_get_platdata(dev);
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debug("%s:\n", __func__);
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writel((XWT_CSR0_WRS_MASK | XWT_CSR0_WDS_MASK | XWT_CSR0_EWDT1_MASK),
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&platdata->regs->twcsr0);
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writel(XWT_CSRX_EWDT2_MASK, &platdata->regs->twcsr1);
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return 0;
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}
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static int xlnx_wdt_probe(struct udevice *dev)
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{
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debug("%s: Probing wdt%u\n", __func__, dev->seq);
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return 0;
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}
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static int xlnx_wdt_ofdata_to_platdata(struct udevice *dev)
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{
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struct xlnx_wdt_platdata *platdata = dev_get_platdata(dev);
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platdata->regs = (struct watchdog_regs *)dev_read_addr(dev);
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if (IS_ERR(platdata->regs))
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return PTR_ERR(platdata->regs);
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platdata->enable_once = dev_read_u32_default(dev,
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"xlnx,wdt-enable-once", 0);
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debug("%s: wdt-enable-once %d\n", __func__, platdata->enable_once);
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return 0;
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}
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static const struct wdt_ops xlnx_wdt_ops = {
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.start = xlnx_wdt_start,
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.reset = xlnx_wdt_reset,
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.stop = xlnx_wdt_stop,
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};
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static const struct udevice_id xlnx_wdt_ids[] = {
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{ .compatible = "xlnx,xps-timebase-wdt-1.00.a", },
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{ .compatible = "xlnx,xps-timebase-wdt-1.01.a", },
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{},
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};
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U_BOOT_DRIVER(xlnx_wdt) = {
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.name = "xlnx_wdt",
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.id = UCLASS_WDT,
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.of_match = xlnx_wdt_ids,
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.probe = xlnx_wdt_probe,
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.platdata_auto_alloc_size = sizeof(struct xlnx_wdt_platdata),
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.ofdata_to_platdata = xlnx_wdt_ofdata_to_platdata,
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.ops = &xlnx_wdt_ops,
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};
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