upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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498 lines
18 KiB
498 lines
18 KiB
/*
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* (C) Copyright 2006-2008
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* Texas Instruments, <www.ti.com>
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* Syed Mohammed Khasim <x0khasim@ti.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _MUX_H_
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#define _MUX_H_
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/*
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* IEN - Input Enable
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* IDIS - Input Disable
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* PTD - Pull type Down
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* PTU - Pull type Up
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* DIS - Pull type selection is inactive
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* EN - Pull type selection is active
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* SB_LOW - Standby mode configuration: Output low-level
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* SB_HI - Standby mode configuration: Output high-level
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* SB_HIZ - Standby mode configuration: Output hi-impedence
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* SB_PD - Standby mode pull-down enabled
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* SB_PU - Standby mode pull-up enabled
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* WKEN - Wakeup input enabled
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* M0 - Mode 0
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*/
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#define IEN (1 << 8)
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#define IDIS (0 << 8)
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#define PTU (1 << 4)
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#define PTD (0 << 4)
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#define EN (1 << 3)
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#define DIS (0 << 3)
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#define SB_LOW (1 << 9)
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#define SB_HI (5 << 9)
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#define SB_HIZ (2 << 9)
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#define SB_PD (1 << 12)
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#define SB_PU (3 << 12)
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#define WKEN (1 << 14)
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#define M0 0
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#define M1 1
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#define M2 2
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#define M3 3
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#define M4 4
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#define M5 5
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#define M6 6
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#define M7 7
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/*
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* To get the actual address the offset has to be added
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* to OMAP34XX_CTRL_BASE
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*/
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/*SDRC*/
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#define CONTROL_PADCONF_SDRC_D0 0x0030
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#define CONTROL_PADCONF_SDRC_D1 0x0032
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#define CONTROL_PADCONF_SDRC_D2 0x0034
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#define CONTROL_PADCONF_SDRC_D3 0x0036
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#define CONTROL_PADCONF_SDRC_D4 0x0038
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#define CONTROL_PADCONF_SDRC_D5 0x003A
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#define CONTROL_PADCONF_SDRC_D6 0x003C
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#define CONTROL_PADCONF_SDRC_D7 0x003E
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#define CONTROL_PADCONF_SDRC_D8 0x0040
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#define CONTROL_PADCONF_SDRC_D9 0x0042
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#define CONTROL_PADCONF_SDRC_D10 0x0044
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#define CONTROL_PADCONF_SDRC_D11 0x0046
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#define CONTROL_PADCONF_SDRC_D12 0x0048
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#define CONTROL_PADCONF_SDRC_D13 0x004A
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#define CONTROL_PADCONF_SDRC_D14 0x004C
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#define CONTROL_PADCONF_SDRC_D15 0x004E
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#define CONTROL_PADCONF_SDRC_D16 0x0050
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#define CONTROL_PADCONF_SDRC_D17 0x0052
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#define CONTROL_PADCONF_SDRC_D18 0x0054
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#define CONTROL_PADCONF_SDRC_D19 0x0056
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#define CONTROL_PADCONF_SDRC_D20 0x0058
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#define CONTROL_PADCONF_SDRC_D21 0x005A
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#define CONTROL_PADCONF_SDRC_D22 0x005C
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#define CONTROL_PADCONF_SDRC_D23 0x005E
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#define CONTROL_PADCONF_SDRC_D24 0x0060
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#define CONTROL_PADCONF_SDRC_D25 0x0062
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#define CONTROL_PADCONF_SDRC_D26 0x0064
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#define CONTROL_PADCONF_SDRC_D27 0x0066
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#define CONTROL_PADCONF_SDRC_D28 0x0068
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#define CONTROL_PADCONF_SDRC_D29 0x006A
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#define CONTROL_PADCONF_SDRC_D30 0x006C
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#define CONTROL_PADCONF_SDRC_D31 0x006E
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#define CONTROL_PADCONF_SDRC_CLK 0x0070
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#define CONTROL_PADCONF_SDRC_DQS0 0x0072
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#define CONTROL_PADCONF_SDRC_DQS1 0x0074
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#define CONTROL_PADCONF_SDRC_DQS2 0x0076
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#define CONTROL_PADCONF_SDRC_DQS3 0x0078
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#define CONTROL_PADCONF_SDRC_BA0 0x05A0
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#define CONTROL_PADCONF_SDRC_BA1 0x05A2
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#define CONTROL_PADCONF_SDRC_A0 0x05A4
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#define CONTROL_PADCONF_SDRC_A1 0x05A6
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#define CONTROL_PADCONF_SDRC_A2 0x05A8
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#define CONTROL_PADCONF_SDRC_A3 0x05AA
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#define CONTROL_PADCONF_SDRC_A4 0x05AC
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#define CONTROL_PADCONF_SDRC_A5 0x05AE
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#define CONTROL_PADCONF_SDRC_A6 0x05B0
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#define CONTROL_PADCONF_SDRC_A7 0x05B2
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#define CONTROL_PADCONF_SDRC_A8 0x05B4
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#define CONTROL_PADCONF_SDRC_A9 0x05B6
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#define CONTROL_PADCONF_SDRC_A10 0x05B8
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#define CONTROL_PADCONF_SDRC_A11 0x05BA
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#define CONTROL_PADCONF_SDRC_A12 0x05BC
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#define CONTROL_PADCONF_SDRC_A13 0x05BE
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#define CONTROL_PADCONF_SDRC_A14 0x05C0
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#define CONTROL_PADCONF_SDRC_NCS0 0x05C2
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#define CONTROL_PADCONF_SDRC_NCS1 0x05C4
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#define CONTROL_PADCONF_SDRC_NCLK 0x05C6
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#define CONTROL_PADCONF_SDRC_NRAS 0x05C8
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#define CONTROL_PADCONF_SDRC_NCAS 0x05CA
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#define CONTROL_PADCONF_SDRC_NWE 0x05CC
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#define CONTROL_PADCONF_SDRC_DM0 0x05CE
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#define CONTROL_PADCONF_SDRC_DM1 0x05D0
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#define CONTROL_PADCONF_SDRC_DM2 0x05D2
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#define CONTROL_PADCONF_SDRC_DM3 0x05D4
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/*GPMC*/
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#define CONTROL_PADCONF_GPMC_A1 0x007A
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#define CONTROL_PADCONF_GPMC_A2 0x007C
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#define CONTROL_PADCONF_GPMC_A3 0x007E
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#define CONTROL_PADCONF_GPMC_A4 0x0080
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#define CONTROL_PADCONF_GPMC_A5 0x0082
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#define CONTROL_PADCONF_GPMC_A6 0x0084
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#define CONTROL_PADCONF_GPMC_A7 0x0086
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#define CONTROL_PADCONF_GPMC_A8 0x0088
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#define CONTROL_PADCONF_GPMC_A9 0x008A
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#define CONTROL_PADCONF_GPMC_A10 0x008C
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#define CONTROL_PADCONF_GPMC_A11 0x0264
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#define CONTROL_PADCONF_GPMC_D0 0x008E
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#define CONTROL_PADCONF_GPMC_D1 0x0090
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#define CONTROL_PADCONF_GPMC_D2 0x0092
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#define CONTROL_PADCONF_GPMC_D3 0x0094
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#define CONTROL_PADCONF_GPMC_D4 0x0096
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#define CONTROL_PADCONF_GPMC_D5 0x0098
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#define CONTROL_PADCONF_GPMC_D6 0x009A
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#define CONTROL_PADCONF_GPMC_D7 0x009C
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#define CONTROL_PADCONF_GPMC_D8 0x009E
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#define CONTROL_PADCONF_GPMC_D9 0x00A0
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#define CONTROL_PADCONF_GPMC_D10 0x00A2
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#define CONTROL_PADCONF_GPMC_D11 0x00A4
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#define CONTROL_PADCONF_GPMC_D12 0x00A6
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#define CONTROL_PADCONF_GPMC_D13 0x00A8
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#define CONTROL_PADCONF_GPMC_D14 0x00AA
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#define CONTROL_PADCONF_GPMC_D15 0x00AC
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#define CONTROL_PADCONF_GPMC_NCS0 0x00AE
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#define CONTROL_PADCONF_GPMC_NCS1 0x00B0
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#define CONTROL_PADCONF_GPMC_NCS2 0x00B2
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#define CONTROL_PADCONF_GPMC_NCS3 0x00B4
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#define CONTROL_PADCONF_GPMC_NCS4 0x00B6
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#define CONTROL_PADCONF_GPMC_NCS5 0x00B8
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#define CONTROL_PADCONF_GPMC_NCS6 0x00BA
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#define CONTROL_PADCONF_GPMC_NCS7 0x00BC
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#define CONTROL_PADCONF_GPMC_CLK 0x00BE
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#define CONTROL_PADCONF_GPMC_NADV_ALE 0x00C0
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#define CONTROL_PADCONF_GPMC_NOE 0x00C2
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#define CONTROL_PADCONF_GPMC_NWE 0x00C4
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#define CONTROL_PADCONF_GPMC_NBE0_CLE 0x00C6
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#define CONTROL_PADCONF_GPMC_NBE1 0x00C8
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#define CONTROL_PADCONF_GPMC_NWP 0x00CA
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#define CONTROL_PADCONF_GPMC_WAIT0 0x00CC
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#define CONTROL_PADCONF_GPMC_WAIT1 0x00CE
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#define CONTROL_PADCONF_GPMC_WAIT2 0x00D0
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#define CONTROL_PADCONF_GPMC_WAIT3 0x00D2
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/*DSS*/
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#define CONTROL_PADCONF_DSS_PCLK 0x00D4
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#define CONTROL_PADCONF_DSS_HSYNC 0x00D6
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#define CONTROL_PADCONF_DSS_VSYNC 0x00D8
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#define CONTROL_PADCONF_DSS_ACBIAS 0x00DA
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#define CONTROL_PADCONF_DSS_DATA0 0x00DC
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#define CONTROL_PADCONF_DSS_DATA1 0x00DE
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#define CONTROL_PADCONF_DSS_DATA2 0x00E0
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#define CONTROL_PADCONF_DSS_DATA3 0x00E2
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#define CONTROL_PADCONF_DSS_DATA4 0x00E4
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#define CONTROL_PADCONF_DSS_DATA5 0x00E6
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#define CONTROL_PADCONF_DSS_DATA6 0x00E8
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#define CONTROL_PADCONF_DSS_DATA7 0x00EA
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#define CONTROL_PADCONF_DSS_DATA8 0x00EC
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#define CONTROL_PADCONF_DSS_DATA9 0x00EE
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#define CONTROL_PADCONF_DSS_DATA10 0x00F0
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#define CONTROL_PADCONF_DSS_DATA11 0x00F2
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#define CONTROL_PADCONF_DSS_DATA12 0x00F4
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#define CONTROL_PADCONF_DSS_DATA13 0x00F6
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#define CONTROL_PADCONF_DSS_DATA14 0x00F8
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#define CONTROL_PADCONF_DSS_DATA15 0x00FA
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#define CONTROL_PADCONF_DSS_DATA16 0x00FC
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#define CONTROL_PADCONF_DSS_DATA17 0x00FE
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#define CONTROL_PADCONF_DSS_DATA18 0x0100
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#define CONTROL_PADCONF_DSS_DATA19 0x0102
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#define CONTROL_PADCONF_DSS_DATA20 0x0104
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#define CONTROL_PADCONF_DSS_DATA21 0x0106
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#define CONTROL_PADCONF_DSS_DATA22 0x0108
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#define CONTROL_PADCONF_DSS_DATA23 0x010A
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/*CAMERA*/
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#define CONTROL_PADCONF_CAM_HS 0x010C
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#define CONTROL_PADCONF_CAM_VS 0x010E
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#define CONTROL_PADCONF_CAM_XCLKA 0x0110
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#define CONTROL_PADCONF_CAM_PCLK 0x0112
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#define CONTROL_PADCONF_CAM_FLD 0x0114
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#define CONTROL_PADCONF_CAM_D0 0x0116
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#define CONTROL_PADCONF_CAM_D1 0x0118
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#define CONTROL_PADCONF_CAM_D2 0x011A
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#define CONTROL_PADCONF_CAM_D3 0x011C
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#define CONTROL_PADCONF_CAM_D4 0x011E
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#define CONTROL_PADCONF_CAM_D5 0x0120
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#define CONTROL_PADCONF_CAM_D6 0x0122
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#define CONTROL_PADCONF_CAM_D7 0x0124
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#define CONTROL_PADCONF_CAM_D8 0x0126
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#define CONTROL_PADCONF_CAM_D9 0x0128
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#define CONTROL_PADCONF_CAM_D10 0x012A
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#define CONTROL_PADCONF_CAM_D11 0x012C
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#define CONTROL_PADCONF_CAM_XCLKB 0x012E
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#define CONTROL_PADCONF_CAM_WEN 0x0130
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#define CONTROL_PADCONF_CAM_STROBE 0x0132
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#define CONTROL_PADCONF_CSI2_DX0 0x0134
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#define CONTROL_PADCONF_CSI2_DY0 0x0136
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#define CONTROL_PADCONF_CSI2_DX1 0x0138
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#define CONTROL_PADCONF_CSI2_DY1 0x013A
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/*Audio Interface */
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#define CONTROL_PADCONF_MCBSP2_FSX 0x013C
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#define CONTROL_PADCONF_MCBSP2_CLKX 0x013E
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#define CONTROL_PADCONF_MCBSP2_DR 0x0140
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#define CONTROL_PADCONF_MCBSP2_DX 0x0142
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#define CONTROL_PADCONF_MMC1_CLK 0x0144
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#define CONTROL_PADCONF_MMC1_CMD 0x0146
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#define CONTROL_PADCONF_MMC1_DAT0 0x0148
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#define CONTROL_PADCONF_MMC1_DAT1 0x014A
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#define CONTROL_PADCONF_MMC1_DAT2 0x014C
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#define CONTROL_PADCONF_MMC1_DAT3 0x014E
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#define CONTROL_PADCONF_MMC1_DAT4 0x0150
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#define CONTROL_PADCONF_MMC1_DAT5 0x0152
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#define CONTROL_PADCONF_MMC1_DAT6 0x0154
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#define CONTROL_PADCONF_MMC1_DAT7 0x0156
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/*Wireless LAN */
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#define CONTROL_PADCONF_MMC2_CLK 0x0158
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#define CONTROL_PADCONF_MMC2_CMD 0x015A
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#define CONTROL_PADCONF_MMC2_DAT0 0x015C
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#define CONTROL_PADCONF_MMC2_DAT1 0x015E
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#define CONTROL_PADCONF_MMC2_DAT2 0x0160
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#define CONTROL_PADCONF_MMC2_DAT3 0x0162
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#define CONTROL_PADCONF_MMC2_DAT4 0x0164
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#define CONTROL_PADCONF_MMC2_DAT5 0x0166
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#define CONTROL_PADCONF_MMC2_DAT6 0x0168
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#define CONTROL_PADCONF_MMC2_DAT7 0x016A
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/*Bluetooth*/
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#define CONTROL_PADCONF_MCBSP3_DX 0x016C
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#define CONTROL_PADCONF_MCBSP3_DR 0x016E
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#define CONTROL_PADCONF_MCBSP3_CLKX 0x0170
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#define CONTROL_PADCONF_MCBSP3_FSX 0x0172
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#define CONTROL_PADCONF_UART2_CTS 0x0174
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#define CONTROL_PADCONF_UART2_RTS 0x0176
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#define CONTROL_PADCONF_UART2_TX 0x0178
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#define CONTROL_PADCONF_UART2_RX 0x017A
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/*Modem Interface */
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#define CONTROL_PADCONF_UART1_TX 0x017C
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#define CONTROL_PADCONF_UART1_RTS 0x017E
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#define CONTROL_PADCONF_UART1_CTS 0x0180
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#define CONTROL_PADCONF_UART1_RX 0x0182
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#define CONTROL_PADCONF_MCBSP4_CLKX 0x0184
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#define CONTROL_PADCONF_MCBSP4_DR 0x0186
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#define CONTROL_PADCONF_MCBSP4_DX 0x0188
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#define CONTROL_PADCONF_MCBSP4_FSX 0x018A
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#define CONTROL_PADCONF_MCBSP1_CLKR 0x018C
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#define CONTROL_PADCONF_MCBSP1_FSR 0x018E
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#define CONTROL_PADCONF_MCBSP1_DX 0x0190
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#define CONTROL_PADCONF_MCBSP1_DR 0x0192
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#define CONTROL_PADCONF_MCBSP_CLKS 0x0194
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#define CONTROL_PADCONF_MCBSP1_FSX 0x0196
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#define CONTROL_PADCONF_MCBSP1_CLKX 0x0198
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/*Serial Interface*/
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#define CONTROL_PADCONF_UART3_CTS_RCTX 0x019A
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#define CONTROL_PADCONF_UART3_RTS_SD 0x019C
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#define CONTROL_PADCONF_UART3_RX_IRRX 0x019E
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#define CONTROL_PADCONF_UART3_TX_IRTX 0x01A0
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#define CONTROL_PADCONF_HSUSB0_CLK 0x01A2
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#define CONTROL_PADCONF_HSUSB0_STP 0x01A4
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#define CONTROL_PADCONF_HSUSB0_DIR 0x01A6
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#define CONTROL_PADCONF_HSUSB0_NXT 0x01A8
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#define CONTROL_PADCONF_HSUSB0_DATA0 0x01AA
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#define CONTROL_PADCONF_HSUSB0_DATA1 0x01AC
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#define CONTROL_PADCONF_HSUSB0_DATA2 0x01AE
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#define CONTROL_PADCONF_HSUSB0_DATA3 0x01B0
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#define CONTROL_PADCONF_HSUSB0_DATA4 0x01B2
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#define CONTROL_PADCONF_HSUSB0_DATA5 0x01B4
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#define CONTROL_PADCONF_HSUSB0_DATA6 0x01B6
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#define CONTROL_PADCONF_HSUSB0_DATA7 0x01B8
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#define CONTROL_PADCONF_I2C1_SCL 0x01BA
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#define CONTROL_PADCONF_I2C1_SDA 0x01BC
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#define CONTROL_PADCONF_I2C2_SCL 0x01BE
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#define CONTROL_PADCONF_I2C2_SDA 0x01C0
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#define CONTROL_PADCONF_I2C3_SCL 0x01C2
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#define CONTROL_PADCONF_I2C3_SDA 0x01C4
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#define CONTROL_PADCONF_I2C4_SCL 0x0A00
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#define CONTROL_PADCONF_I2C4_SDA 0x0A02
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#define CONTROL_PADCONF_HDQ_SIO 0x01C6
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#define CONTROL_PADCONF_MCSPI1_CLK 0x01C8
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#define CONTROL_PADCONF_MCSPI1_SIMO 0x01CA
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#define CONTROL_PADCONF_MCSPI1_SOMI 0x01CC
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#define CONTROL_PADCONF_MCSPI1_CS0 0x01CE
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#define CONTROL_PADCONF_MCSPI1_CS1 0x01D0
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#define CONTROL_PADCONF_MCSPI1_CS2 0x01D2
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#define CONTROL_PADCONF_MCSPI1_CS3 0x01D4
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#define CONTROL_PADCONF_MCSPI2_CLK 0x01D6
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#define CONTROL_PADCONF_MCSPI2_SIMO 0x01D8
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#define CONTROL_PADCONF_MCSPI2_SOMI 0x01DA
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#define CONTROL_PADCONF_MCSPI2_CS0 0x01DC
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#define CONTROL_PADCONF_MCSPI2_CS1 0x01DE
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/*Control and debug */
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#define CONTROL_PADCONF_SYS_32K 0x0A04
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#define CONTROL_PADCONF_SYS_CLKREQ 0x0A06
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#define CONTROL_PADCONF_SYS_NIRQ 0x01E0
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#define CONTROL_PADCONF_SYS_BOOT0 0x0A0A
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#define CONTROL_PADCONF_SYS_BOOT1 0x0A0C
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#define CONTROL_PADCONF_SYS_BOOT2 0x0A0E
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#define CONTROL_PADCONF_SYS_BOOT3 0x0A10
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#define CONTROL_PADCONF_SYS_BOOT4 0x0A12
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#define CONTROL_PADCONF_SYS_BOOT5 0x0A14
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#define CONTROL_PADCONF_SYS_BOOT6 0x0A16
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#define CONTROL_PADCONF_SYS_OFF_MODE 0x0A18
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#define CONTROL_PADCONF_SYS_CLKOUT1 0x0A1A
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#define CONTROL_PADCONF_SYS_CLKOUT2 0x01E2
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#define CONTROL_PADCONF_JTAG_NTRST 0x0A1C
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#define CONTROL_PADCONF_JTAG_TCK 0x0A1E
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#define CONTROL_PADCONF_JTAG_TMS 0x0A20
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#define CONTROL_PADCONF_JTAG_TDI 0x0A22
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#define CONTROL_PADCONF_JTAG_EMU0 0x0A24
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#define CONTROL_PADCONF_JTAG_EMU1 0x0A26
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#define CONTROL_PADCONF_ETK_CLK 0x0A28
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#define CONTROL_PADCONF_ETK_CTL 0x0A2A
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#define CONTROL_PADCONF_ETK_D0 0x0A2C
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#define CONTROL_PADCONF_ETK_D1 0x0A2E
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#define CONTROL_PADCONF_ETK_D2 0x0A30
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#define CONTROL_PADCONF_ETK_D3 0x0A32
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#define CONTROL_PADCONF_ETK_D4 0x0A34
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#define CONTROL_PADCONF_ETK_D5 0x0A36
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#define CONTROL_PADCONF_ETK_D6 0x0A38
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#define CONTROL_PADCONF_ETK_D7 0x0A3A
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#define CONTROL_PADCONF_ETK_D8 0x0A3C
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#define CONTROL_PADCONF_ETK_D9 0x0A3E
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#define CONTROL_PADCONF_ETK_D10 0x0A40
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#define CONTROL_PADCONF_ETK_D11 0x0A42
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#define CONTROL_PADCONF_ETK_D12 0x0A44
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#define CONTROL_PADCONF_ETK_D13 0x0A46
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#define CONTROL_PADCONF_ETK_D14 0x0A48
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#define CONTROL_PADCONF_ETK_D15 0x0A4A
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#define CONTROL_PADCONF_ETK_CLK_ES2 0x05D8
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#define CONTROL_PADCONF_ETK_CTL_ES2 0x05DA
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#define CONTROL_PADCONF_ETK_D0_ES2 0x05DC
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#define CONTROL_PADCONF_ETK_D1_ES2 0x05DE
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#define CONTROL_PADCONF_ETK_D2_ES2 0x05E0
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#define CONTROL_PADCONF_ETK_D3_ES2 0x05E2
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#define CONTROL_PADCONF_ETK_D4_ES2 0x05E4
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#define CONTROL_PADCONF_ETK_D5_ES2 0x05E6
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#define CONTROL_PADCONF_ETK_D6_ES2 0x05E8
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#define CONTROL_PADCONF_ETK_D7_ES2 0x05EA
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#define CONTROL_PADCONF_ETK_D8_ES2 0x05EC
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#define CONTROL_PADCONF_ETK_D9_ES2 0x05EE
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#define CONTROL_PADCONF_ETK_D10_ES2 0x05F0
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#define CONTROL_PADCONF_ETK_D11_ES2 0x05F2
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#define CONTROL_PADCONF_ETK_D12_ES2 0x05F4
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#define CONTROL_PADCONF_ETK_D13_ES2 0x05F6
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#define CONTROL_PADCONF_ETK_D14_ES2 0x05F8
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#define CONTROL_PADCONF_ETK_D15_ES2 0x05FA
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#define CONTROL_PADCONF_JTAG_RTCK 0x0A4E
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#define CONTROL_PADCONF_JTAG_TDO 0x0A50
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/*Die to Die */
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#define CONTROL_PADCONF_D2D_MCAD0 0x01E4
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#define CONTROL_PADCONF_D2D_MCAD1 0x01E6
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#define CONTROL_PADCONF_D2D_MCAD2 0x01E8
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#define CONTROL_PADCONF_D2D_MCAD3 0x01EA
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#define CONTROL_PADCONF_D2D_MCAD4 0x01EC
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#define CONTROL_PADCONF_D2D_MCAD5 0x01EE
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#define CONTROL_PADCONF_D2D_MCAD6 0x01F0
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#define CONTROL_PADCONF_D2D_MCAD7 0x01F2
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#define CONTROL_PADCONF_D2D_MCAD8 0x01F4
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#define CONTROL_PADCONF_D2D_MCAD9 0x01F6
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#define CONTROL_PADCONF_D2D_MCAD10 0x01F8
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#define CONTROL_PADCONF_D2D_MCAD11 0x01FA
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#define CONTROL_PADCONF_D2D_MCAD12 0x01FC
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#define CONTROL_PADCONF_D2D_MCAD13 0x01FE
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#define CONTROL_PADCONF_D2D_MCAD14 0x0200
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#define CONTROL_PADCONF_D2D_MCAD15 0x0202
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#define CONTROL_PADCONF_D2D_MCAD16 0x0204
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#define CONTROL_PADCONF_D2D_MCAD17 0x0206
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#define CONTROL_PADCONF_D2D_MCAD18 0x0208
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#define CONTROL_PADCONF_D2D_MCAD19 0x020A
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#define CONTROL_PADCONF_D2D_MCAD20 0x020C
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#define CONTROL_PADCONF_D2D_MCAD21 0x020E
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#define CONTROL_PADCONF_D2D_MCAD22 0x0210
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#define CONTROL_PADCONF_D2D_MCAD23 0x0212
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#define CONTROL_PADCONF_D2D_MCAD24 0x0214
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#define CONTROL_PADCONF_D2D_MCAD25 0x0216
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#define CONTROL_PADCONF_D2D_MCAD26 0x0218
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#define CONTROL_PADCONF_D2D_MCAD27 0x021A
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#define CONTROL_PADCONF_D2D_MCAD28 0x021C
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#define CONTROL_PADCONF_D2D_MCAD29 0x021E
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#define CONTROL_PADCONF_D2D_MCAD30 0x0220
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#define CONTROL_PADCONF_D2D_MCAD31 0x0222
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#define CONTROL_PADCONF_D2D_MCAD32 0x0224
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#define CONTROL_PADCONF_D2D_MCAD33 0x0226
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#define CONTROL_PADCONF_D2D_MCAD34 0x0228
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#define CONTROL_PADCONF_D2D_MCAD35 0x022A
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#define CONTROL_PADCONF_D2D_MCAD36 0x022C
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#define CONTROL_PADCONF_D2D_CLK26MI 0x022E
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#define CONTROL_PADCONF_D2D_NRESPWRON 0x0230
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#define CONTROL_PADCONF_D2D_NRESWARM 0x0232
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#define CONTROL_PADCONF_D2D_ARM9NIRQ 0x0234
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#define CONTROL_PADCONF_D2D_UMA2P6FIQ 0x0236
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#define CONTROL_PADCONF_D2D_SPINT 0x0238
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#define CONTROL_PADCONF_D2D_FRINT 0x023A
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#define CONTROL_PADCONF_D2D_DMAREQ0 0x023C
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#define CONTROL_PADCONF_D2D_DMAREQ1 0x023E
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#define CONTROL_PADCONF_D2D_DMAREQ2 0x0240
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#define CONTROL_PADCONF_D2D_DMAREQ3 0x0242
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#define CONTROL_PADCONF_D2D_N3GTRST 0x0244
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#define CONTROL_PADCONF_D2D_N3GTDI 0x0246
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#define CONTROL_PADCONF_D2D_N3GTDO 0x0248
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#define CONTROL_PADCONF_D2D_N3GTMS 0x024A
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#define CONTROL_PADCONF_D2D_N3GTCK 0x024C
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#define CONTROL_PADCONF_D2D_N3GRTCK 0x024E
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#define CONTROL_PADCONF_D2D_MSTDBY 0x0250
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#define CONTROL_PADCONF_D2D_SWAKEUP 0x0A4C
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#define CONTROL_PADCONF_D2D_IDLEREQ 0x0252
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#define CONTROL_PADCONF_D2D_IDLEACK 0x0254
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#define CONTROL_PADCONF_D2D_MWRITE 0x0256
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#define CONTROL_PADCONF_D2D_SWRITE 0x0258
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#define CONTROL_PADCONF_D2D_MREAD 0x025A
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#define CONTROL_PADCONF_D2D_SREAD 0x025C
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#define CONTROL_PADCONF_D2D_MBUSFLAG 0x025E
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#define CONTROL_PADCONF_D2D_SBUSFLAG 0x0260
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#define CONTROL_PADCONF_SDRC_CKE0 0x0262
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#define CONTROL_PADCONF_SDRC_CKE1 0x0264
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/* AM3517 specific mux configuration */
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#define CONTROL_PADCONF_SYS_NRESWARM 0x0A08
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/* CCDC */
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#define CONTROL_PADCONF_CCDC_PCLK 0x01E4
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#define CONTROL_PADCONF_CCDC_FIELD 0x01E6
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#define CONTROL_PADCONF_CCDC_HD 0x01E8
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#define CONTROL_PADCONF_CCDC_VD 0x01EA
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#define CONTROL_PADCONF_CCDC_WEN 0x01EC
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#define CONTROL_PADCONF_CCDC_DATA0 0x01EE
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#define CONTROL_PADCONF_CCDC_DATA1 0x01F0
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#define CONTROL_PADCONF_CCDC_DATA2 0x01F2
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#define CONTROL_PADCONF_CCDC_DATA3 0x01F4
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#define CONTROL_PADCONF_CCDC_DATA4 0x01F6
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#define CONTROL_PADCONF_CCDC_DATA5 0x01F8
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#define CONTROL_PADCONF_CCDC_DATA6 0x01FA
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#define CONTROL_PADCONF_CCDC_DATA7 0x01FC
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/* RMII */
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#define CONTROL_PADCONF_RMII_MDIO_DATA 0x01FE
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#define CONTROL_PADCONF_RMII_MDIO_CLK 0x0200
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#define CONTROL_PADCONF_RMII_RXD0 0x0202
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#define CONTROL_PADCONF_RMII_RXD1 0x0204
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#define CONTROL_PADCONF_RMII_CRS_DV 0x0206
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#define CONTROL_PADCONF_RMII_RXER 0x0208
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#define CONTROL_PADCONF_RMII_TXD0 0x020A
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#define CONTROL_PADCONF_RMII_TXD1 0x020C
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#define CONTROL_PADCONF_RMII_TXEN 0x020E
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#define CONTROL_PADCONF_RMII_50MHZ_CLK 0x0210
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#define CONTROL_PADCONF_USB0_DRVBUS 0x0212
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/* CAN */
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#define CONTROL_PADCONF_HECC1_TXD 0x0214
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#define CONTROL_PADCONF_HECC1_RXD 0x0216
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#define CONTROL_PADCONF_SYS_BOOT7 0x0218
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#define CONTROL_PADCONF_SDRC_DQS0N 0x021A
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#define CONTROL_PADCONF_SDRC_DQS1N 0x021C
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#define CONTROL_PADCONF_SDRC_DQS2N 0x021E
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#define CONTROL_PADCONF_SDRC_DQS3N 0x0220
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#define CONTROL_PADCONF_STRBEN_DLY0 0x0222
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#define CONTROL_PADCONF_STRBEN_DLY1 0x0224
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#define CONTROL_PADCONF_SYS_BOOT8 0x0226
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/* AM/DM37xx specific */
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#define CONTROL_PADCONF_GPIO112 0x0134
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#define CONTROL_PADCONF_GPIO113 0x0136
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#define CONTROL_PADCONF_GPIO114 0x0138
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#define CONTROL_PADCONF_GPIO115 0x013A
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#define CONTROL_PADCONF_GPIO127 0x0A54
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#define CONTROL_PADCONF_GPIO126 0x0A56
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#define CONTROL_PADCONF_GPIO128 0x0A58
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#define CONTROL_PADCONF_GPIO129 0x0A5A
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/* AM/DM37xx specific: gpio_127, gpio_127 and gpio_129 require configuration
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* of the extended drain cells */
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#define OMAP34XX_CTRL_WKUP_CTRL (OMAP34XX_CTRL_BASE + 0x0A5C)
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#define OMAP34XX_CTRL_WKUP_CTRL_GPIO_IO_PWRDNZ (1<<6)
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#define MUX_VAL(OFFSET, VALUE)\
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writew((VALUE), OMAP34XX_CTRL_BASE + (OFFSET));
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#define CP(x) (CONTROL_PADCONF_##x)
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#endif
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