upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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45 lines
1.1 KiB
45 lines
1.1 KiB
/**
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* This file is intended to provide backward
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* compatibility for main osService/OSSL
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* APIs.
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*
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* It shall be phased out gradually and users
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* are strongly recommended to use IX_OSAL API.
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*
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* @par
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* IXP400 SW Release version 2.0
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*
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* -- Copyright Notice --
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*
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* @par
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* Copyright 2001-2005, Intel Corporation.
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* All rights reserved.
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*
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* @par
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* SPDX-License-Identifier: BSD-3-Clause
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* @par
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* -- End of Copyright Notice --
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*/
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#ifndef IX_OSAL_BACKWARD_CACHE_MMU_H
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#define IX_OSAL_BACKWARD_CACHE_MMU_H
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#ifdef IX_OSAL_CACHED
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#define IX_ACC_CACHE_ENABLED
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#endif
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#define IX_XSCALE_CACHE_LINE_SIZE IX_OSAL_CACHE_LINE_SIZE
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#define IX_ACC_DRV_DMA_MALLOC(size) IX_OSAL_CACHE_DMA_MALLOC(size)
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#define IX_ACC_DRV_DMA_FREE(ptr,size) IX_OSAL_CACHE_DMA_FREE(ptr)
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#define IX_MMU_VIRTUAL_TO_PHYSICAL_TRANSLATION(addr) IX_OSAL_MMU_VIRT_TO_PHYS(addr)
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#define IX_MMU_PHYSICAL_TO_VIRTUAL_TRANSLATION(addr) IX_OSAL_MMU_PHYS_TO_VIRT(addr)
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#define IX_ACC_DATA_CACHE_INVALIDATE(addr,size) IX_OSAL_CACHE_INVALIDATE(addr, size)
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#define IX_ACC_DATA_CACHE_FLUSH(addr,size) IX_OSAL_CACHE_FLUSH(addr,size)
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#endif /* IX_OSAL_BACKWARD_CACHE_MMU_H */
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