upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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72 lines
1.3 KiB
72 lines
1.3 KiB
/**
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* @file IxQMgrQAccess_p.h
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*
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* @author Intel Corporation
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* @date 30-Oct-2001
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*
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* @brief QAccess private header file
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*
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*
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* @par
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* IXP400 SW Release version 2.0
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*
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* -- Copyright Notice --
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*
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* @par
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* Copyright 2001-2005, Intel Corporation.
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* All rights reserved.
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*
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* @par
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* SPDX-License-Identifier: BSD-3-Clause
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* @par
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* -- End of Copyright Notice --
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*/
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#ifndef IXQMGRQACCESS_P_H
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#define IXQMGRQACCESS_P_H
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/*
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* User defined header files
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*/
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#include "IxQMgr.h"
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/*
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* Global variables declarations.
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*/
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extern volatile UINT32 * ixQMgrAqmIfQueAccRegAddr[];
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/*
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* Initialise the Queue Access component
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*/
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void
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ixQMgrQAccessInit (void);
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/*
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* read the remainder of a multi-word queue entry
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* (the first word is already read)
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*/
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IX_STATUS
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ixQMgrQReadMWordsMinus1 (IxQMgrQId qId,
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UINT32 *entry);
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/*
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* Fast access : pop a q entry from a single word queue
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*/
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extern __inline__ UINT32 ixQMgrQAccessPop(IxQMgrQId qId);
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extern __inline__ UINT32 ixQMgrQAccessPop(IxQMgrQId qId)
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{
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return *(ixQMgrAqmIfQueAccRegAddr[qId]);
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}
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/*
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* Fast access : push a q entry in a single word queue
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*/
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extern __inline__ void ixQMgrQAccessPush(IxQMgrQId qId, UINT32 entry);
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extern __inline__ void ixQMgrQAccessPush(IxQMgrQId qId, UINT32 entry)
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{
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*(ixQMgrAqmIfQueAccRegAddr[qId]) = entry;
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}
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#endif/*IXQMGRQACCESS_P_H*/
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