upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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88 lines
2.1 KiB
88 lines
2.1 KiB
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2006
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* Markus Klotzbuecher, DENX Software Engineering <mk@denx.de>
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*/
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#include <common.h>
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#if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT)
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# if defined(CONFIG_CPU_MONAHANS) || defined(CONFIG_CPU_PXA27X)
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#include <asm/arch/pxa-regs.h>
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#include <asm/io.h>
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#include <usb.h>
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int usb_cpu_init(void)
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{
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#if defined(CONFIG_CPU_MONAHANS)
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/* Enable USB host clock. */
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writel(readl(CKENA) | CKENA_2_USBHOST | CKENA_20_UDC, CKENA);
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udelay(100);
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#endif
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#if defined(CONFIG_CPU_PXA27X)
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/* Enable USB host clock. */
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writel(readl(CKEN) | CKEN10_USBHOST, CKEN);
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#endif
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#if defined(CONFIG_CPU_MONAHANS)
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/* Configure Port 2 for Host (USB Client Registers) */
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writel(0x3000c, UP2OCR);
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#endif
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writel(readl(UHCHR) | UHCHR_FHR, UHCHR);
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mdelay(11);
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writel(readl(UHCHR) & ~UHCHR_FHR, UHCHR);
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writel(readl(UHCHR) | UHCHR_FSBIR, UHCHR);
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while (readl(UHCHR) & UHCHR_FSBIR)
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udelay(1);
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#if defined(CONFIG_CPU_MONAHANS) || defined(CONFIG_PXA27X)
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writel(readl(UHCHR) & ~UHCHR_SSEP0, UHCHR);
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#endif
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#if defined(CONFIG_CPU_PXA27X)
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writel(readl(UHCHR) & ~UHCHR_SSEP2, UHCHR);
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#endif
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writel(readl(UHCHR) & ~(UHCHR_SSEP1 | UHCHR_SSE), UHCHR);
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return 0;
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}
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int usb_cpu_stop(void)
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{
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writel(readl(UHCHR) | UHCHR_FHR, UHCHR);
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udelay(11);
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writel(readl(UHCHR) & ~UHCHR_FHR, UHCHR);
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writel(readl(UHCCOMS) | UHCCOMS_HCR, UHCCOMS);
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udelay(10);
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#if defined(CONFIG_CPU_MONAHANS) || defined(CONFIG_PXA27X)
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writel(readl(UHCHR) | UHCHR_SSEP0, UHCHR);
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#endif
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#if defined(CONFIG_CPU_PXA27X)
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writel(readl(UHCHR) | UHCHR_SSEP2, UHCHR);
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#endif
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writel(readl(UHCHR) | UHCHR_SSEP1 | UHCHR_SSE, UHCHR);
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#if defined(CONFIG_CPU_MONAHANS)
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/* Disable USB host clock. */
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writel(readl(CKENA) & ~(CKENA_2_USBHOST | CKENA_20_UDC), CKENA);
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udelay(100);
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#endif
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#if defined(CONFIG_CPU_PXA27X)
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/* Disable USB host clock. */
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writel(readl(CKEN) & ~CKEN10_USBHOST, CKEN);
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#endif
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return 0;
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}
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int usb_cpu_init_fail(void)
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{
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return usb_cpu_stop();
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}
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# endif /* defined(CONFIG_CPU_MONAHANS) || defined(CONFIG_CPU_PXA27X) */
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#endif /* defined(CONFIG_USB_OHCI) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT) */
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