upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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44 lines
1.3 KiB
44 lines
1.3 KiB
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2017 Beckhoff Automation GmbH & Co. KG
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* Patrick Bruenn <p.bruenn@beckhoff.com>
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*/
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#include <common.h>
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DECLARE_GLOBAL_DATA_PTR;
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phys_size_t get_effective_memsize(void)
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{
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/*
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* WARNING: We must override get_effective_memsize() function here
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* to report only the size of the first DRAM bank. This is to make
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* U-Boot relocator place U-Boot into valid memory, that is, at the
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* end of the first DRAM bank. If we did not override this function
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* like so, U-Boot would be placed at the address of the first DRAM
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* bank + total DRAM size - sizeof(uboot), which in the setup where
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* each DRAM bank contains 512MiB of DRAM would result in placing
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* U-Boot into invalid memory area close to the end of the first
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* DRAM bank.
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*/
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return get_ram_size((void *)PHYS_SDRAM_1, 1 << 30);
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}
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int dram_init(void)
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{
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gd->ram_size = get_ram_size((void *)PHYS_SDRAM_1, 1 << 30);
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gd->ram_size += get_ram_size((void *)PHYS_SDRAM_2, 1 << 30);
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return 0;
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}
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int dram_init_banksize(void)
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{
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gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
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gd->bd->bi_dram[0].size = get_ram_size((void *)PHYS_SDRAM_1, 1 << 30);
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gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
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gd->bd->bi_dram[1].size = get_ram_size((void *)PHYS_SDRAM_2, 1 << 30);
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return 0;
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}
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