upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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64 lines
1.4 KiB
64 lines
1.4 KiB
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2016-2018 Socionext Inc.
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* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
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*/
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#include <common.h>
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#include <fdt_support.h>
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#include <fdtdec.h>
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#include <jffs2/load_kernel.h>
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#include <mtd_node.h>
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#include <linux/kernel.h>
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#include <linux/printk.h>
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#include "soc-info.h"
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/*
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* The DRAM PHY requires 64 byte scratch area in each DRAM channel
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* for its dynamic PHY training feature.
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*/
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static int uniphier_ld20_fdt_mem_rsv(void *fdt, bd_t *bd)
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{
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unsigned long rsv_addr;
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const unsigned long rsv_size = 64;
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int i, ret;
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if (!IS_ENABLED(CONFIG_ARCH_UNIPHIER_LD20) ||
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uniphier_get_soc_id() != UNIPHIER_LD20_ID)
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return 0;
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for (i = 0; i < ARRAY_SIZE(bd->bi_dram); i++) {
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if (!bd->bi_dram[i].size)
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continue;
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rsv_addr = bd->bi_dram[i].start + bd->bi_dram[i].size;
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rsv_addr -= rsv_size;
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ret = fdt_add_mem_rsv(fdt, rsv_addr, rsv_size);
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if (ret)
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return -ENOSPC;
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pr_notice(" Reserved memory region for DRAM PHY training: addr=%lx size=%lx\n",
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rsv_addr, rsv_size);
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}
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return 0;
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}
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int ft_board_setup(void *fdt, bd_t *bd)
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{
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static const struct node_info nodes[] = {
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{ "socionext,uniphier-denali-nand-v5a", MTD_DEV_TYPE_NAND },
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{ "socionext,uniphier-denali-nand-v5b", MTD_DEV_TYPE_NAND },
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};
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int ret;
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fdt_fixup_mtdparts(fdt, nodes, ARRAY_SIZE(nodes));
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ret = uniphier_ld20_fdt_mem_rsv(fdt, bd);
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if (ret)
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return ret;
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return 0;
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}
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