upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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113 lines
2.4 KiB
113 lines
2.4 KiB
/*
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* Porting to u-boot:
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*
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* (C) Copyright 2011
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* Stefano Babic, DENX Software Engineering, sbabic@denx.de.
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*
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* Copyright (C) 2008-2009 MontaVista Software Inc.
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* Copyright (C) 2008-2009 Texas Instruments Inc
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*
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* Based on the LCD driver for TI Avalanche processors written by
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* Ajay Singh and Shalom Hai.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef DA8XX_FB_H
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#define DA8XX_FB_H
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enum panel_type {
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QVGA = 0
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};
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enum panel_shade {
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MONOCHROME = 0,
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COLOR_ACTIVE,
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COLOR_PASSIVE,
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};
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enum raster_load_mode {
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LOAD_DATA = 1,
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LOAD_PALETTE,
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};
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struct display_panel {
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enum panel_type panel_type; /* QVGA */
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int max_bpp;
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int min_bpp;
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enum panel_shade panel_shade;
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};
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struct da8xx_panel {
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const char name[25]; /* Full name <vendor>_<model> */
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unsigned short width;
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unsigned short height;
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int hfp; /* Horizontal front porch */
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int hbp; /* Horizontal back porch */
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int hsw; /* Horizontal Sync Pulse Width */
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int vfp; /* Vertical front porch */
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int vbp; /* Vertical back porch */
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int vsw; /* Vertical Sync Pulse Width */
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unsigned int pxl_clk; /* Pixel clock */
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unsigned char invert_pxl_clk; /* Invert Pixel clock */
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};
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struct da8xx_lcdc_platform_data {
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const char manu_name[10];
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void *controller_data;
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const char type[25];
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void (*panel_power_ctrl)(int);
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};
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struct lcd_ctrl_config {
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const struct display_panel *p_disp_panel;
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/* AC Bias Pin Frequency */
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int ac_bias;
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/* AC Bias Pin Transitions per Interrupt */
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int ac_bias_intrpt;
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/* DMA burst size */
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int dma_burst_sz;
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/* Bits per pixel */
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int bpp;
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/* FIFO DMA Request Delay */
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int fdd;
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/* TFT Alternative Signal Mapping (Only for active) */
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unsigned char tft_alt_mode;
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/* 12 Bit Per Pixel (5-6-5) Mode (Only for passive) */
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unsigned char stn_565_mode;
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/* Mono 8-bit Mode: 1=D0-D7 or 0=D0-D3 */
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unsigned char mono_8bit_mode;
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/* Invert line clock */
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unsigned char invert_line_clock;
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/* Invert frame clock */
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unsigned char invert_frm_clock;
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/* Horizontal and Vertical Sync Edge: 0=rising 1=falling */
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unsigned char sync_edge;
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/* Horizontal and Vertical Sync: Control: 0=ignore */
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unsigned char sync_ctrl;
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/* Raster Data Order Select: 1=Most-to-least 0=Least-to-most */
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unsigned char raster_order;
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};
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struct lcd_sync_arg {
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int back_porch;
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int front_porch;
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int pulse_width;
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};
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void da8xx_video_init(const struct da8xx_panel *panel, int bits_pixel);
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#endif /* ifndef DA8XX_FB_H */
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