upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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150 lines
3.9 KiB
150 lines
3.9 KiB
/*
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* (C) Copyright 2007-2008
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* Stelian Pop <stelian@popies.net>
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* Lead Tech Design <www.leadtechdesign.com>
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*
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* Copyright (C) 2009
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* Albin Tonnerre, Free Electrons <albin.tonnerre@free-electrons.com>
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*
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* Configuation settings for the Calao TNY-A9260 and TNY-A9G20 boards
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*
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* SoC must be defined first, before hardware.h is included.
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* In this case SoC is defined in boards.cfg.
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*/
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#include <asm/hardware.h>
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#if defined(CONFIG_TNY_A9260_NANDFLASH) || defined(CONFIG_TNY_A9G20_NANDFLASH)
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#define CONFIG_ENV_IS_IN_NAND
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#else
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#define CONFIG_ENV_IS_IN_EEPROM
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#endif
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/* Define actual evaluation board type from used processor type */
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#ifdef CONFIG_AT91SAM9G20
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# define CONFIG_TNY_A9G20
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# define MACH_TYPE_TNY_A9G20 2059
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# define CONFIG_MACH_TYPE MACH_TYPE_TNY_A9G20
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#else
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# define CONFIG_TNY_A9260
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# define MACH_TYPE_TNY_A9260 2058
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# define CONFIG_MACH_TYPE MACH_TYPE_TNY_A9260
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#endif
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/* ARM asynchronous clock */
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#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */
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#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* 12 MHz crystal */
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#define CONFIG_ARCH_CPU_INIT
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#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
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#define CONFIG_SETUP_MEMORY_TAGS
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#define CONFIG_INITRD_TAG
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#define CONFIG_SKIP_LOWLEVEL_INIT
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/*
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* Hardware drivers
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*/
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#define CONFIG_ATMEL_LEGACY
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#define CONFIG_AT91_GPIO
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#define CONFIG_ATMEL_USART
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#define CONFIG_USART_BASE ATMEL_BASE_DBGU
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#define CONFIG_USART_ID ATMEL_ID_SYS
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#define CONFIG_BAUDRATE 115200
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#define CONFIG_BOOTDELAY 3
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/*
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* Command line configuration.
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*/
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#include <config_cmd_default.h>
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#undef CONFIG_CMD_BDI
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#undef CONFIG_CMD_FPGA
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#undef CONFIG_CMD_IMI
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#undef CONFIG_CMD_IMLS
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#undef CONFIG_CMD_LOADS
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#undef CONFIG_CMD_NET
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#undef CONFIG_CMD_NFS
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#undef CONFIG_CMD_SOURCE
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#undef CONFIG_CMD_USB
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/* SDRAM */
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#define CONFIG_NR_DRAM_BANKS 1
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#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1
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#define CONFIG_SYS_SDRAM_SIZE 0x04000000 /* 64 megs */
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# define CONFIG_SYS_INIT_SP_ADDR \
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(ATMEL_BASE_SRAM1 + 0x1000 - GENERATED_GBL_DATA_SIZE)
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/* SPI EEPROM */
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#define CONFIG_SPI
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#define CONFIG_CMD_SPI
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#define CONFIG_ATMEL_SPI
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#define CONFIG_CMD_EEPROM
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#define CONFIG_SPI_M95XXX
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#define CONFIG_SYS_EEPROM_SIZE 0x10000
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#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5
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/* NAND flash */
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#define CONFIG_CMD_NAND
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#define CONFIG_NAND_ATMEL
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#define CONFIG_SYS_MAX_NAND_DEVICE 1
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#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3
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#define CONFIG_SYS_NAND_DBW_8
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/* our ALE is AD21 */
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#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
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/* our CLE is AD22 */
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#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
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#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14
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#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC13
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/* NOR flash - no real flash on this board */
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#define CONFIG_SYS_NO_FLASH
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#define CONFIG_DOS_PARTITION
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#define CONFIG_CMD_FAT
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#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
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#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
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#define CONFIG_SYS_MEMTEST_END 0x23e00000
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/* Env in EEPROM, bootstrap + u-boot in NAND*/
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#ifdef CONFIG_ENV_IS_IN_EEPROM
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#define CONFIG_ENV_OFFSET 0x20
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#define CONFIG_ENV_SIZE 0x1000
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#endif
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/* Env, bootstrap and u-boot in NAND */
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#ifdef CONFIG_ENV_IS_IN_NAND
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#define CONFIG_ENV_OFFSET 0x60000
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#define CONFIG_ENV_OFFSET_REDUND 0x80000
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#define CONFIG_ENV_SIZE 0x20000
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#endif
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#define CONFIG_BOOTCOMMAND "nboot 0x21000000 0 400000"
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#define CONFIG_BOOTARGS "console=ttyS0,115200 " \
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"root=/dev/mtdblock1 " \
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"mtdparts=atmel_nand:16M(kernel)ro," \
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"120M(rootfs),-(other) " \
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"rw rootfstype=jffs2"
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#define CONFIG_SYS_PROMPT "U-Boot> "
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#define CONFIG_SYS_CBSIZE 256
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#define CONFIG_SYS_MAXARGS 16
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
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#define CONFIG_SYS_LONGHELP
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#define CONFIG_CMDLINE_EDITING
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/*
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* Size of malloc() pool
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*/
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#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128 * 1024, 0x1000)
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#endif
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