upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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1301 lines
32 KiB
1301 lines
32 KiB
/*
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* Freescale Three Speed Ethernet Controller driver
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*
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* This software may be used and distributed according to the
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* terms of the GNU Public License, Version 2, incorporated
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* herein by reference.
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*
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* Copyright 2004 Freescale Semiconductor.
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* (C) Copyright 2003, Motorola, Inc.
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* author Andy Fleming
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*
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*/
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#include <config.h>
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#include <common.h>
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#include <malloc.h>
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#include <net.h>
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#include <command.h>
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#if defined(CONFIG_TSEC_ENET)
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#include "tsec.h"
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#include "miiphy.h"
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DECLARE_GLOBAL_DATA_PTR;
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#define TX_BUF_CNT 2
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static uint rxIdx; /* index of the current RX buffer */
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static uint txIdx; /* index of the current TX buffer */
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typedef volatile struct rtxbd {
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txbd8_t txbd[TX_BUF_CNT];
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rxbd8_t rxbd[PKTBUFSRX];
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} RTXBD;
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struct tsec_info_struct {
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unsigned int phyaddr;
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u32 flags;
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unsigned int phyregidx;
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};
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/* The tsec_info structure contains 3 values which the
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* driver uses to determine how to operate a given ethernet
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* device. The information needed is:
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* phyaddr - The address of the PHY which is attached to
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* the given device.
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*
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* flags - This variable indicates whether the device
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* supports gigabit speed ethernet, and whether it should be
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* in reduced mode.
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*
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* phyregidx - This variable specifies which ethernet device
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* controls the MII Management registers which are connected
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* to the PHY. For now, only TSEC1 (index 0) has
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* access to the PHYs, so all of the entries have "0".
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*
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* The values specified in the table are taken from the board's
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* config file in include/configs/. When implementing a new
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* board with ethernet capability, it is necessary to define:
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* TSECn_PHY_ADDR
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* TSECn_PHYIDX
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*
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* for n = 1,2,3, etc. And for FEC:
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* FEC_PHY_ADDR
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* FEC_PHYIDX
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*/
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static struct tsec_info_struct tsec_info[] = {
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#if defined(CONFIG_MPC85XX_TSEC1) || defined(CONFIG_MPC83XX_TSEC1)
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{TSEC1_PHY_ADDR, TSEC_GIGABIT, TSEC1_PHYIDX},
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#elif defined(CONFIG_MPC86XX_TSEC1)
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{TSEC1_PHY_ADDR, TSEC_GIGABIT | TSEC_REDUCED, TSEC1_PHYIDX},
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#else
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{0, 0, 0},
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#endif
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#if defined(CONFIG_MPC85XX_TSEC2) || defined(CONFIG_MPC83XX_TSEC2)
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{TSEC2_PHY_ADDR, TSEC_GIGABIT, TSEC2_PHYIDX},
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#elif defined(CONFIG_MPC86XX_TSEC2)
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{TSEC2_PHY_ADDR, TSEC_GIGABIT | TSEC_REDUCED, TSEC2_PHYIDX},
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#else
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{0, 0, 0},
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#endif
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#ifdef CONFIG_MPC85XX_FEC
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{FEC_PHY_ADDR, 0, FEC_PHYIDX},
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#else
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#if defined(CONFIG_MPC85XX_TSEC3) || defined(CONFIG_MPC83XX_TSEC3) || defined(CONFIG_MPC86XX_TSEC3)
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{TSEC3_PHY_ADDR, TSEC_GIGABIT | TSEC_REDUCED, TSEC3_PHYIDX},
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#else
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{0, 0, 0},
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#endif
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#if defined(CONFIG_MPC85XX_TSEC4) || defined(CONFIG_MPC83XX_TSEC4) || defined(CONFIG_MPC86XX_TSEC4)
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{TSEC4_PHY_ADDR, TSEC_GIGABIT | TSEC_REDUCED, TSEC4_PHYIDX},
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#else
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{0, 0, 0},
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#endif
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#endif
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};
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#define MAXCONTROLLERS (4)
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static int relocated = 0;
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static struct tsec_private *privlist[MAXCONTROLLERS];
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#ifdef __GNUC__
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static RTXBD rtx __attribute__ ((aligned(8)));
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#else
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#error "rtx must be 64-bit aligned"
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#endif
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static int tsec_send(struct eth_device *dev,
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volatile void *packet, int length);
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static int tsec_recv(struct eth_device *dev);
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static int tsec_init(struct eth_device *dev, bd_t * bd);
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static void tsec_halt(struct eth_device *dev);
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static void init_registers(volatile tsec_t * regs);
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static void startup_tsec(struct eth_device *dev);
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static int init_phy(struct eth_device *dev);
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void write_phy_reg(struct tsec_private *priv, uint regnum, uint value);
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uint read_phy_reg(struct tsec_private *priv, uint regnum);
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struct phy_info *get_phy_info(struct eth_device *dev);
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void phy_run_commands(struct tsec_private *priv, struct phy_cmd *cmd);
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static void adjust_link(struct eth_device *dev);
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static void relocate_cmds(void);
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static int tsec_miiphy_write(char *devname, unsigned char addr,
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unsigned char reg, unsigned short value);
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static int tsec_miiphy_read(char *devname, unsigned char addr,
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unsigned char reg, unsigned short *value);
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/* Initialize device structure. Returns success if PHY
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* initialization succeeded (i.e. if it recognizes the PHY)
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*/
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int tsec_initialize(bd_t * bis, int index, char *devname)
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{
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struct eth_device *dev;
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int i;
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struct tsec_private *priv;
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dev = (struct eth_device *)malloc(sizeof *dev);
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if (NULL == dev)
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return 0;
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memset(dev, 0, sizeof *dev);
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priv = (struct tsec_private *)malloc(sizeof(*priv));
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if (NULL == priv)
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return 0;
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privlist[index] = priv;
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priv->regs = (volatile tsec_t *)(TSEC_BASE_ADDR + index * TSEC_SIZE);
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priv->phyregs = (volatile tsec_t *)(TSEC_BASE_ADDR +
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tsec_info[index].phyregidx *
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TSEC_SIZE);
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priv->phyaddr = tsec_info[index].phyaddr;
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priv->flags = tsec_info[index].flags;
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sprintf(dev->name, devname);
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dev->iobase = 0;
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dev->priv = priv;
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dev->init = tsec_init;
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dev->halt = tsec_halt;
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dev->send = tsec_send;
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dev->recv = tsec_recv;
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/* Tell u-boot to get the addr from the env */
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for (i = 0; i < 6; i++)
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dev->enetaddr[i] = 0;
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eth_register(dev);
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/* Reset the MAC */
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priv->regs->maccfg1 |= MACCFG1_SOFT_RESET;
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priv->regs->maccfg1 &= ~(MACCFG1_SOFT_RESET);
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#if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII) \
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&& !defined(BITBANGMII)
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miiphy_register(dev->name, tsec_miiphy_read, tsec_miiphy_write);
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#endif
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/* Try to initialize PHY here, and return */
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return init_phy(dev);
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}
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/* Initializes data structures and registers for the controller,
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* and brings the interface up. Returns the link status, meaning
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* that it returns success if the link is up, failure otherwise.
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* This allows u-boot to find the first active controller.
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*/
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int tsec_init(struct eth_device *dev, bd_t * bd)
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{
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uint tempval;
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char tmpbuf[MAC_ADDR_LEN];
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int i;
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struct tsec_private *priv = (struct tsec_private *)dev->priv;
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volatile tsec_t *regs = priv->regs;
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/* Make sure the controller is stopped */
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tsec_halt(dev);
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/* Init MACCFG2. Defaults to GMII */
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regs->maccfg2 = MACCFG2_INIT_SETTINGS;
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/* Init ECNTRL */
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regs->ecntrl = ECNTRL_INIT_SETTINGS;
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/* Copy the station address into the address registers.
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* Backwards, because little endian MACS are dumb */
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for (i = 0; i < MAC_ADDR_LEN; i++) {
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tmpbuf[MAC_ADDR_LEN - 1 - i] = dev->enetaddr[i];
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}
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regs->macstnaddr1 = *((uint *) (tmpbuf));
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tempval = *((uint *) (tmpbuf + 4));
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regs->macstnaddr2 = tempval;
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/* reset the indices to zero */
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rxIdx = 0;
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txIdx = 0;
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/* Clear out (for the most part) the other registers */
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init_registers(regs);
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/* Ready the device for tx/rx */
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startup_tsec(dev);
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/* If there's no link, fail */
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return priv->link;
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}
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/* Write value to the device's PHY through the registers
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* specified in priv, modifying the register specified in regnum.
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* It will wait for the write to be done (or for a timeout to
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* expire) before exiting
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*/
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void write_phy_reg(struct tsec_private *priv, uint regnum, uint value)
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{
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volatile tsec_t *regbase = priv->phyregs;
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uint phyid = priv->phyaddr;
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int timeout = 1000000;
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regbase->miimadd = (phyid << 8) | regnum;
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regbase->miimcon = value;
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asm("sync");
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timeout = 1000000;
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while ((regbase->miimind & MIIMIND_BUSY) && timeout--) ;
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}
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/* Reads register regnum on the device's PHY through the
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* registers specified in priv. It lowers and raises the read
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* command, and waits for the data to become valid (miimind
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* notvalid bit cleared), and the bus to cease activity (miimind
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* busy bit cleared), and then returns the value
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*/
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uint read_phy_reg(struct tsec_private *priv, uint regnum)
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{
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uint value;
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volatile tsec_t *regbase = priv->phyregs;
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uint phyid = priv->phyaddr;
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/* Put the address of the phy, and the register
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* number into MIIMADD */
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regbase->miimadd = (phyid << 8) | regnum;
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/* Clear the command register, and wait */
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regbase->miimcom = 0;
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asm("sync");
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/* Initiate a read command, and wait */
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regbase->miimcom = MIIM_READ_COMMAND;
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asm("sync");
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/* Wait for the the indication that the read is done */
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while ((regbase->miimind & (MIIMIND_NOTVALID | MIIMIND_BUSY))) ;
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/* Grab the value read from the PHY */
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value = regbase->miimstat;
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return value;
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}
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/* Discover which PHY is attached to the device, and configure it
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* properly. If the PHY is not recognized, then return 0
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* (failure). Otherwise, return 1
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*/
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static int init_phy(struct eth_device *dev)
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{
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struct tsec_private *priv = (struct tsec_private *)dev->priv;
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struct phy_info *curphy;
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volatile tsec_t *regs = (volatile tsec_t *)(TSEC_BASE_ADDR);
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/* Assign a Physical address to the TBI */
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regs->tbipa = TBIPA_VALUE;
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regs = (volatile tsec_t *)(TSEC_BASE_ADDR + TSEC_SIZE);
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regs->tbipa = TBIPA_VALUE;
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asm("sync");
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/* Reset MII (due to new addresses) */
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priv->phyregs->miimcfg = MIIMCFG_RESET;
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asm("sync");
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priv->phyregs->miimcfg = MIIMCFG_INIT_VALUE;
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asm("sync");
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while (priv->phyregs->miimind & MIIMIND_BUSY) ;
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if (0 == relocated)
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relocate_cmds();
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/* Get the cmd structure corresponding to the attached
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* PHY */
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curphy = get_phy_info(dev);
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if (curphy == NULL) {
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priv->phyinfo = NULL;
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printf("%s: No PHY found\n", dev->name);
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return 0;
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}
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priv->phyinfo = curphy;
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phy_run_commands(priv, priv->phyinfo->config);
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return 1;
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}
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/*
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* Returns which value to write to the control register.
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* For 10/100, the value is slightly different
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*/
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uint mii_cr_init(uint mii_reg, struct tsec_private * priv)
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{
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if (priv->flags & TSEC_GIGABIT)
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return MIIM_CONTROL_INIT;
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else
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return MIIM_CR_INIT;
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}
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/* Parse the status register for link, and then do
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* auto-negotiation
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*/
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uint mii_parse_sr(uint mii_reg, struct tsec_private * priv)
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{
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/*
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* Wait if PHY is capable of autonegotiation and autonegotiation
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* is not complete.
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*/
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mii_reg = read_phy_reg(priv, MIIM_STATUS);
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if ((mii_reg & PHY_BMSR_AUTN_ABLE)
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&& !(mii_reg & PHY_BMSR_AUTN_COMP)) {
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int i = 0;
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puts("Waiting for PHY auto negotiation to complete");
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while (!((mii_reg & PHY_BMSR_AUTN_COMP)
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&& (mii_reg & MIIM_STATUS_LINK))) {
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/*
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* Timeout reached ?
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*/
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if (i > PHY_AUTONEGOTIATE_TIMEOUT) {
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puts(" TIMEOUT !\n");
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priv->link = 0;
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return 0;
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}
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if ((i++ % 1000) == 0) {
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putc('.');
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}
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udelay(1000); /* 1 ms */
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mii_reg = read_phy_reg(priv, MIIM_STATUS);
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}
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puts(" done\n");
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priv->link = 1;
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udelay(500000); /* another 500 ms (results in faster booting) */
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} else {
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priv->link = 1;
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}
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return 0;
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}
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/* Parse the 88E1011's status register for speed and duplex
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* information
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*/
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uint mii_parse_88E1011_psr(uint mii_reg, struct tsec_private * priv)
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{
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uint speed;
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mii_reg = read_phy_reg(priv, MIIM_88E1011_PHY_STATUS);
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if (!((mii_reg & MIIM_88E1011_PHYSTAT_SPDDONE) &&
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(mii_reg & MIIM_88E1011_PHYSTAT_LINK))) {
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int i = 0;
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puts("Waiting for PHY realtime link");
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while (!((mii_reg & MIIM_88E1011_PHYSTAT_SPDDONE) &&
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(mii_reg & MIIM_88E1011_PHYSTAT_LINK))) {
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/*
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* Timeout reached ?
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*/
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if (i > PHY_AUTONEGOTIATE_TIMEOUT) {
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puts(" TIMEOUT !\n");
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priv->link = 0;
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break;
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}
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if ((i++ % 1000) == 0) {
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putc('.');
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}
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udelay(1000); /* 1 ms */
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mii_reg = read_phy_reg(priv, MIIM_88E1011_PHY_STATUS);
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}
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puts(" done\n");
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udelay(500000); /* another 500 ms (results in faster booting) */
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}
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if (mii_reg & MIIM_88E1011_PHYSTAT_DUPLEX)
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priv->duplexity = 1;
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else
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priv->duplexity = 0;
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speed = (mii_reg & MIIM_88E1011_PHYSTAT_SPEED);
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switch (speed) {
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case MIIM_88E1011_PHYSTAT_GBIT:
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priv->speed = 1000;
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break;
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case MIIM_88E1011_PHYSTAT_100:
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priv->speed = 100;
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break;
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default:
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priv->speed = 10;
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}
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return 0;
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}
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/* Parse the cis8201's status register for speed and duplex
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* information
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*/
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uint mii_parse_cis8201(uint mii_reg, struct tsec_private * priv)
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{
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uint speed;
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if (mii_reg & MIIM_CIS8201_AUXCONSTAT_DUPLEX)
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priv->duplexity = 1;
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else
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priv->duplexity = 0;
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speed = mii_reg & MIIM_CIS8201_AUXCONSTAT_SPEED;
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switch (speed) {
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case MIIM_CIS8201_AUXCONSTAT_GBIT:
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priv->speed = 1000;
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break;
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case MIIM_CIS8201_AUXCONSTAT_100:
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priv->speed = 100;
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break;
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default:
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priv->speed = 10;
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break;
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}
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return 0;
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}
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/* Parse the vsc8244's status register for speed and duplex
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* information
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*/
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uint mii_parse_vsc8244(uint mii_reg, struct tsec_private * priv)
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{
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uint speed;
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if (mii_reg & MIIM_VSC8244_AUXCONSTAT_DUPLEX)
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priv->duplexity = 1;
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else
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priv->duplexity = 0;
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speed = mii_reg & MIIM_VSC8244_AUXCONSTAT_SPEED;
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switch (speed) {
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case MIIM_VSC8244_AUXCONSTAT_GBIT:
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priv->speed = 1000;
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break;
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case MIIM_VSC8244_AUXCONSTAT_100:
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priv->speed = 100;
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break;
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default:
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priv->speed = 10;
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break;
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}
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return 0;
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}
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/* Parse the DM9161's status register for speed and duplex
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* information
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*/
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uint mii_parse_dm9161_scsr(uint mii_reg, struct tsec_private * priv)
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{
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if (mii_reg & (MIIM_DM9161_SCSR_100F | MIIM_DM9161_SCSR_100H))
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priv->speed = 100;
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else
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priv->speed = 10;
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if (mii_reg & (MIIM_DM9161_SCSR_100F | MIIM_DM9161_SCSR_10F))
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priv->duplexity = 1;
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else
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priv->duplexity = 0;
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|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* Hack to write all 4 PHYs with the LED values
|
|
*/
|
|
uint mii_cis8204_fixled(uint mii_reg, struct tsec_private * priv)
|
|
{
|
|
uint phyid;
|
|
volatile tsec_t *regbase = priv->phyregs;
|
|
int timeout = 1000000;
|
|
|
|
for (phyid = 0; phyid < 4; phyid++) {
|
|
regbase->miimadd = (phyid << 8) | mii_reg;
|
|
regbase->miimcon = MIIM_CIS8204_SLEDCON_INIT;
|
|
asm("sync");
|
|
|
|
timeout = 1000000;
|
|
while ((regbase->miimind & MIIMIND_BUSY) && timeout--) ;
|
|
}
|
|
|
|
return MIIM_CIS8204_SLEDCON_INIT;
|
|
}
|
|
|
|
uint mii_cis8204_setmode(uint mii_reg, struct tsec_private * priv)
|
|
{
|
|
if (priv->flags & TSEC_REDUCED)
|
|
return MIIM_CIS8204_EPHYCON_INIT | MIIM_CIS8204_EPHYCON_RGMII;
|
|
else
|
|
return MIIM_CIS8204_EPHYCON_INIT;
|
|
}
|
|
|
|
/* Initialized required registers to appropriate values, zeroing
|
|
* those we don't care about (unless zero is bad, in which case,
|
|
* choose a more appropriate value)
|
|
*/
|
|
static void init_registers(volatile tsec_t * regs)
|
|
{
|
|
/* Clear IEVENT */
|
|
regs->ievent = IEVENT_INIT_CLEAR;
|
|
|
|
regs->imask = IMASK_INIT_CLEAR;
|
|
|
|
regs->hash.iaddr0 = 0;
|
|
regs->hash.iaddr1 = 0;
|
|
regs->hash.iaddr2 = 0;
|
|
regs->hash.iaddr3 = 0;
|
|
regs->hash.iaddr4 = 0;
|
|
regs->hash.iaddr5 = 0;
|
|
regs->hash.iaddr6 = 0;
|
|
regs->hash.iaddr7 = 0;
|
|
|
|
regs->hash.gaddr0 = 0;
|
|
regs->hash.gaddr1 = 0;
|
|
regs->hash.gaddr2 = 0;
|
|
regs->hash.gaddr3 = 0;
|
|
regs->hash.gaddr4 = 0;
|
|
regs->hash.gaddr5 = 0;
|
|
regs->hash.gaddr6 = 0;
|
|
regs->hash.gaddr7 = 0;
|
|
|
|
regs->rctrl = 0x00000000;
|
|
|
|
/* Init RMON mib registers */
|
|
memset((void *)&(regs->rmon), 0, sizeof(rmon_mib_t));
|
|
|
|
regs->rmon.cam1 = 0xffffffff;
|
|
regs->rmon.cam2 = 0xffffffff;
|
|
|
|
regs->mrblr = MRBLR_INIT_SETTINGS;
|
|
|
|
regs->minflr = MINFLR_INIT_SETTINGS;
|
|
|
|
regs->attr = ATTR_INIT_SETTINGS;
|
|
regs->attreli = ATTRELI_INIT_SETTINGS;
|
|
|
|
}
|
|
|
|
/* Configure maccfg2 based on negotiated speed and duplex
|
|
* reported by PHY handling code
|
|
*/
|
|
static void adjust_link(struct eth_device *dev)
|
|
{
|
|
struct tsec_private *priv = (struct tsec_private *)dev->priv;
|
|
volatile tsec_t *regs = priv->regs;
|
|
|
|
if (priv->link) {
|
|
if (priv->duplexity != 0)
|
|
regs->maccfg2 |= MACCFG2_FULL_DUPLEX;
|
|
else
|
|
regs->maccfg2 &= ~(MACCFG2_FULL_DUPLEX);
|
|
|
|
switch (priv->speed) {
|
|
case 1000:
|
|
regs->maccfg2 = ((regs->maccfg2 & ~(MACCFG2_IF))
|
|
| MACCFG2_GMII);
|
|
break;
|
|
case 100:
|
|
case 10:
|
|
regs->maccfg2 = ((regs->maccfg2 & ~(MACCFG2_IF))
|
|
| MACCFG2_MII);
|
|
|
|
/* Set R100 bit in all modes although
|
|
* it is only used in RGMII mode
|
|
*/
|
|
if (priv->speed == 100)
|
|
regs->ecntrl |= ECNTRL_R100;
|
|
else
|
|
regs->ecntrl &= ~(ECNTRL_R100);
|
|
break;
|
|
default:
|
|
printf("%s: Speed was bad\n", dev->name);
|
|
break;
|
|
}
|
|
|
|
printf("Speed: %d, %s duplex\n", priv->speed,
|
|
(priv->duplexity) ? "full" : "half");
|
|
|
|
} else {
|
|
printf("%s: No link.\n", dev->name);
|
|
}
|
|
}
|
|
|
|
/* Set up the buffers and their descriptors, and bring up the
|
|
* interface
|
|
*/
|
|
static void startup_tsec(struct eth_device *dev)
|
|
{
|
|
int i;
|
|
struct tsec_private *priv = (struct tsec_private *)dev->priv;
|
|
volatile tsec_t *regs = priv->regs;
|
|
|
|
/* Point to the buffer descriptors */
|
|
regs->tbase = (unsigned int)(&rtx.txbd[txIdx]);
|
|
regs->rbase = (unsigned int)(&rtx.rxbd[rxIdx]);
|
|
|
|
/* Initialize the Rx Buffer descriptors */
|
|
for (i = 0; i < PKTBUFSRX; i++) {
|
|
rtx.rxbd[i].status = RXBD_EMPTY;
|
|
rtx.rxbd[i].length = 0;
|
|
rtx.rxbd[i].bufPtr = (uint) NetRxPackets[i];
|
|
}
|
|
rtx.rxbd[PKTBUFSRX - 1].status |= RXBD_WRAP;
|
|
|
|
/* Initialize the TX Buffer Descriptors */
|
|
for (i = 0; i < TX_BUF_CNT; i++) {
|
|
rtx.txbd[i].status = 0;
|
|
rtx.txbd[i].length = 0;
|
|
rtx.txbd[i].bufPtr = 0;
|
|
}
|
|
rtx.txbd[TX_BUF_CNT - 1].status |= TXBD_WRAP;
|
|
|
|
/* Start up the PHY */
|
|
if(priv->phyinfo)
|
|
phy_run_commands(priv, priv->phyinfo->startup);
|
|
adjust_link(dev);
|
|
|
|
/* Enable Transmit and Receive */
|
|
regs->maccfg1 |= (MACCFG1_RX_EN | MACCFG1_TX_EN);
|
|
|
|
/* Tell the DMA it is clear to go */
|
|
regs->dmactrl |= DMACTRL_INIT_SETTINGS;
|
|
regs->tstat = TSTAT_CLEAR_THALT;
|
|
regs->dmactrl &= ~(DMACTRL_GRS | DMACTRL_GTS);
|
|
}
|
|
|
|
/* This returns the status bits of the device. The return value
|
|
* is never checked, and this is what the 8260 driver did, so we
|
|
* do the same. Presumably, this would be zero if there were no
|
|
* errors
|
|
*/
|
|
static int tsec_send(struct eth_device *dev, volatile void *packet, int length)
|
|
{
|
|
int i;
|
|
int result = 0;
|
|
struct tsec_private *priv = (struct tsec_private *)dev->priv;
|
|
volatile tsec_t *regs = priv->regs;
|
|
|
|
/* Find an empty buffer descriptor */
|
|
for (i = 0; rtx.txbd[txIdx].status & TXBD_READY; i++) {
|
|
if (i >= TOUT_LOOP) {
|
|
debug("%s: tsec: tx buffers full\n", dev->name);
|
|
return result;
|
|
}
|
|
}
|
|
|
|
rtx.txbd[txIdx].bufPtr = (uint) packet;
|
|
rtx.txbd[txIdx].length = length;
|
|
rtx.txbd[txIdx].status |=
|
|
(TXBD_READY | TXBD_LAST | TXBD_CRC | TXBD_INTERRUPT);
|
|
|
|
/* Tell the DMA to go */
|
|
regs->tstat = TSTAT_CLEAR_THALT;
|
|
|
|
/* Wait for buffer to be transmitted */
|
|
for (i = 0; rtx.txbd[txIdx].status & TXBD_READY; i++) {
|
|
if (i >= TOUT_LOOP) {
|
|
debug("%s: tsec: tx error\n", dev->name);
|
|
return result;
|
|
}
|
|
}
|
|
|
|
txIdx = (txIdx + 1) % TX_BUF_CNT;
|
|
result = rtx.txbd[txIdx].status & TXBD_STATS;
|
|
|
|
return result;
|
|
}
|
|
|
|
static int tsec_recv(struct eth_device *dev)
|
|
{
|
|
int length;
|
|
struct tsec_private *priv = (struct tsec_private *)dev->priv;
|
|
volatile tsec_t *regs = priv->regs;
|
|
|
|
while (!(rtx.rxbd[rxIdx].status & RXBD_EMPTY)) {
|
|
|
|
length = rtx.rxbd[rxIdx].length;
|
|
|
|
/* Send the packet up if there were no errors */
|
|
if (!(rtx.rxbd[rxIdx].status & RXBD_STATS)) {
|
|
NetReceive(NetRxPackets[rxIdx], length - 4);
|
|
} else {
|
|
printf("Got error %x\n",
|
|
(rtx.rxbd[rxIdx].status & RXBD_STATS));
|
|
}
|
|
|
|
rtx.rxbd[rxIdx].length = 0;
|
|
|
|
/* Set the wrap bit if this is the last element in the list */
|
|
rtx.rxbd[rxIdx].status =
|
|
RXBD_EMPTY | (((rxIdx + 1) == PKTBUFSRX) ? RXBD_WRAP : 0);
|
|
|
|
rxIdx = (rxIdx + 1) % PKTBUFSRX;
|
|
}
|
|
|
|
if (regs->ievent & IEVENT_BSY) {
|
|
regs->ievent = IEVENT_BSY;
|
|
regs->rstat = RSTAT_CLEAR_RHALT;
|
|
}
|
|
|
|
return -1;
|
|
|
|
}
|
|
|
|
/* Stop the interface */
|
|
static void tsec_halt(struct eth_device *dev)
|
|
{
|
|
struct tsec_private *priv = (struct tsec_private *)dev->priv;
|
|
volatile tsec_t *regs = priv->regs;
|
|
|
|
regs->dmactrl &= ~(DMACTRL_GRS | DMACTRL_GTS);
|
|
regs->dmactrl |= (DMACTRL_GRS | DMACTRL_GTS);
|
|
|
|
while (!(regs->ievent & (IEVENT_GRSC | IEVENT_GTSC))) ;
|
|
|
|
regs->maccfg1 &= ~(MACCFG1_TX_EN | MACCFG1_RX_EN);
|
|
|
|
/* Shut down the PHY, as needed */
|
|
if(priv->phyinfo)
|
|
phy_run_commands(priv, priv->phyinfo->shutdown);
|
|
}
|
|
|
|
struct phy_info phy_info_M88E1011S = {
|
|
0x01410c6,
|
|
"Marvell 88E1011S",
|
|
4,
|
|
(struct phy_cmd[]){ /* config */
|
|
/* Reset and configure the PHY */
|
|
{MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
|
|
{0x1d, 0x1f, NULL},
|
|
{0x1e, 0x200c, NULL},
|
|
{0x1d, 0x5, NULL},
|
|
{0x1e, 0x0, NULL},
|
|
{0x1e, 0x100, NULL},
|
|
{MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
|
|
{MIIM_ANAR, MIIM_ANAR_INIT, NULL},
|
|
{MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
|
|
{MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
|
|
{miim_end,}
|
|
},
|
|
(struct phy_cmd[]){ /* startup */
|
|
/* Status is read once to clear old link state */
|
|
{MIIM_STATUS, miim_read, NULL},
|
|
/* Auto-negotiate */
|
|
{MIIM_STATUS, miim_read, &mii_parse_sr},
|
|
/* Read the status */
|
|
{MIIM_88E1011_PHY_STATUS, miim_read,
|
|
&mii_parse_88E1011_psr},
|
|
{miim_end,}
|
|
},
|
|
(struct phy_cmd[]){ /* shutdown */
|
|
{miim_end,}
|
|
},
|
|
};
|
|
|
|
struct phy_info phy_info_M88E1111S = {
|
|
0x01410cc,
|
|
"Marvell 88E1111S",
|
|
4,
|
|
(struct phy_cmd[]){ /* config */
|
|
/* Reset and configure the PHY */
|
|
{MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
|
|
{0x1d, 0x1f, NULL},
|
|
{0x1e, 0x200c, NULL},
|
|
{0x1d, 0x5, NULL},
|
|
{0x1e, 0x0, NULL},
|
|
{0x1e, 0x100, NULL},
|
|
{0x14, 0x0cd2, NULL}, /* Delay RGMII TX and RX */
|
|
{MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
|
|
{MIIM_ANAR, MIIM_ANAR_INIT, NULL},
|
|
{MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
|
|
{MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
|
|
{miim_end,}
|
|
},
|
|
(struct phy_cmd[]){ /* startup */
|
|
/* Status is read once to clear old link state */
|
|
{MIIM_STATUS, miim_read, NULL},
|
|
/* Auto-negotiate */
|
|
{MIIM_STATUS, miim_read, &mii_parse_sr},
|
|
/* Read the status */
|
|
{MIIM_88E1011_PHY_STATUS, miim_read,
|
|
&mii_parse_88E1011_psr},
|
|
{miim_end,}
|
|
},
|
|
(struct phy_cmd[]){ /* shutdown */
|
|
{miim_end,}
|
|
},
|
|
};
|
|
|
|
static unsigned int m88e1145_setmode(uint mii_reg, struct tsec_private *priv)
|
|
{
|
|
uint mii_data = read_phy_reg(priv, mii_reg);
|
|
|
|
/* Setting MIIM_88E1145_PHY_EXT_CR */
|
|
if (priv->flags & TSEC_REDUCED)
|
|
return mii_data |
|
|
MIIM_M88E1145_RGMII_RX_DELAY | MIIM_M88E1145_RGMII_TX_DELAY;
|
|
else
|
|
return mii_data;
|
|
}
|
|
|
|
static struct phy_info phy_info_M88E1145 = {
|
|
0x01410cd,
|
|
"Marvell 88E1145",
|
|
4,
|
|
(struct phy_cmd[]){ /* config */
|
|
/* Errata E0, E1 */
|
|
{29, 0x001b, NULL},
|
|
{30, 0x418f, NULL},
|
|
{29, 0x0016, NULL},
|
|
{30, 0xa2da, NULL},
|
|
|
|
/* Reset and configure the PHY */
|
|
{MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
|
|
{MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
|
|
{MIIM_ANAR, MIIM_ANAR_INIT, NULL},
|
|
{MIIM_88E1011_PHY_SCR, MIIM_88E1011_PHY_MDI_X_AUTO,
|
|
NULL},
|
|
{MIIM_88E1145_PHY_EXT_CR, 0, &m88e1145_setmode},
|
|
{MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
|
|
{MIIM_CONTROL, MIIM_CONTROL_INIT, NULL},
|
|
{miim_end,}
|
|
},
|
|
(struct phy_cmd[]){ /* startup */
|
|
/* Status is read once to clear old link state */
|
|
{MIIM_STATUS, miim_read, NULL},
|
|
/* Auto-negotiate */
|
|
{MIIM_STATUS, miim_read, &mii_parse_sr},
|
|
{MIIM_88E1111_PHY_LED_CONTROL,
|
|
MIIM_88E1111_PHY_LED_DIRECT, NULL},
|
|
/* Read the Status */
|
|
{MIIM_88E1011_PHY_STATUS, miim_read,
|
|
&mii_parse_88E1011_psr},
|
|
{miim_end,}
|
|
},
|
|
(struct phy_cmd[]){ /* shutdown */
|
|
{miim_end,}
|
|
},
|
|
};
|
|
|
|
struct phy_info phy_info_cis8204 = {
|
|
0x3f11,
|
|
"Cicada Cis8204",
|
|
6,
|
|
(struct phy_cmd[]){ /* config */
|
|
/* Override PHY config settings */
|
|
{MIIM_CIS8201_AUX_CONSTAT,
|
|
MIIM_CIS8201_AUXCONSTAT_INIT, NULL},
|
|
/* Configure some basic stuff */
|
|
{MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
|
|
{MIIM_CIS8204_SLED_CON, MIIM_CIS8204_SLEDCON_INIT,
|
|
&mii_cis8204_fixled},
|
|
{MIIM_CIS8204_EPHY_CON, MIIM_CIS8204_EPHYCON_INIT,
|
|
&mii_cis8204_setmode},
|
|
{miim_end,}
|
|
},
|
|
(struct phy_cmd[]){ /* startup */
|
|
/* Read the Status (2x to make sure link is right) */
|
|
{MIIM_STATUS, miim_read, NULL},
|
|
/* Auto-negotiate */
|
|
{MIIM_STATUS, miim_read, &mii_parse_sr},
|
|
/* Read the status */
|
|
{MIIM_CIS8201_AUX_CONSTAT, miim_read,
|
|
&mii_parse_cis8201},
|
|
{miim_end,}
|
|
},
|
|
(struct phy_cmd[]){ /* shutdown */
|
|
{miim_end,}
|
|
},
|
|
};
|
|
|
|
/* Cicada 8201 */
|
|
struct phy_info phy_info_cis8201 = {
|
|
0xfc41,
|
|
"CIS8201",
|
|
4,
|
|
(struct phy_cmd[]){ /* config */
|
|
/* Override PHY config settings */
|
|
{MIIM_CIS8201_AUX_CONSTAT,
|
|
MIIM_CIS8201_AUXCONSTAT_INIT, NULL},
|
|
/* Set up the interface mode */
|
|
{MIIM_CIS8201_EXT_CON1, MIIM_CIS8201_EXTCON1_INIT,
|
|
NULL},
|
|
/* Configure some basic stuff */
|
|
{MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
|
|
{miim_end,}
|
|
},
|
|
(struct phy_cmd[]){ /* startup */
|
|
/* Read the Status (2x to make sure link is right) */
|
|
{MIIM_STATUS, miim_read, NULL},
|
|
/* Auto-negotiate */
|
|
{MIIM_STATUS, miim_read, &mii_parse_sr},
|
|
/* Read the status */
|
|
{MIIM_CIS8201_AUX_CONSTAT, miim_read,
|
|
&mii_parse_cis8201},
|
|
{miim_end,}
|
|
},
|
|
(struct phy_cmd[]){ /* shutdown */
|
|
{miim_end,}
|
|
},
|
|
};
|
|
struct phy_info phy_info_VSC8244 = {
|
|
0x3f1b,
|
|
"Vitesse VSC8244",
|
|
6,
|
|
(struct phy_cmd[]){ /* config */
|
|
/* Override PHY config settings */
|
|
/* Configure some basic stuff */
|
|
{MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
|
|
{miim_end,}
|
|
},
|
|
(struct phy_cmd[]){ /* startup */
|
|
/* Read the Status (2x to make sure link is right) */
|
|
{MIIM_STATUS, miim_read, NULL},
|
|
/* Auto-negotiate */
|
|
{MIIM_STATUS, miim_read, &mii_parse_sr},
|
|
/* Read the status */
|
|
{MIIM_VSC8244_AUX_CONSTAT, miim_read,
|
|
&mii_parse_vsc8244},
|
|
{miim_end,}
|
|
},
|
|
(struct phy_cmd[]){ /* shutdown */
|
|
{miim_end,}
|
|
},
|
|
};
|
|
|
|
struct phy_info phy_info_dm9161 = {
|
|
0x0181b88,
|
|
"Davicom DM9161E",
|
|
4,
|
|
(struct phy_cmd[]){ /* config */
|
|
{MIIM_CONTROL, MIIM_DM9161_CR_STOP, NULL},
|
|
/* Do not bypass the scrambler/descrambler */
|
|
{MIIM_DM9161_SCR, MIIM_DM9161_SCR_INIT, NULL},
|
|
/* Clear 10BTCSR to default */
|
|
{MIIM_DM9161_10BTCSR, MIIM_DM9161_10BTCSR_INIT,
|
|
NULL},
|
|
/* Configure some basic stuff */
|
|
{MIIM_CONTROL, MIIM_CR_INIT, NULL},
|
|
/* Restart Auto Negotiation */
|
|
{MIIM_CONTROL, MIIM_DM9161_CR_RSTAN, NULL},
|
|
{miim_end,}
|
|
},
|
|
(struct phy_cmd[]){ /* startup */
|
|
/* Status is read once to clear old link state */
|
|
{MIIM_STATUS, miim_read, NULL},
|
|
/* Auto-negotiate */
|
|
{MIIM_STATUS, miim_read, &mii_parse_sr},
|
|
/* Read the status */
|
|
{MIIM_DM9161_SCSR, miim_read,
|
|
&mii_parse_dm9161_scsr},
|
|
{miim_end,}
|
|
},
|
|
(struct phy_cmd[]){ /* shutdown */
|
|
{miim_end,}
|
|
},
|
|
};
|
|
|
|
uint mii_parse_lxt971_sr2(uint mii_reg, struct tsec_private *priv)
|
|
{
|
|
unsigned int speed;
|
|
if (priv->link) {
|
|
speed = mii_reg & MIIM_LXT971_SR2_SPEED_MASK;
|
|
|
|
switch (speed) {
|
|
case MIIM_LXT971_SR2_10HDX:
|
|
priv->speed = 10;
|
|
priv->duplexity = 0;
|
|
break;
|
|
case MIIM_LXT971_SR2_10FDX:
|
|
priv->speed = 10;
|
|
priv->duplexity = 1;
|
|
break;
|
|
case MIIM_LXT971_SR2_100HDX:
|
|
priv->speed = 100;
|
|
priv->duplexity = 0;
|
|
default:
|
|
priv->speed = 100;
|
|
priv->duplexity = 1;
|
|
break;
|
|
}
|
|
} else {
|
|
priv->speed = 0;
|
|
priv->duplexity = 0;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct phy_info phy_info_lxt971 = {
|
|
0x0001378e,
|
|
"LXT971",
|
|
4,
|
|
(struct phy_cmd[]){ /* config */
|
|
{MIIM_CR, MIIM_CR_INIT, mii_cr_init}, /* autonegotiate */
|
|
{miim_end,}
|
|
},
|
|
(struct phy_cmd[]){ /* startup - enable interrupts */
|
|
/* { 0x12, 0x00f2, NULL }, */
|
|
{MIIM_STATUS, miim_read, NULL},
|
|
{MIIM_STATUS, miim_read, &mii_parse_sr},
|
|
{MIIM_LXT971_SR2, miim_read, &mii_parse_lxt971_sr2},
|
|
{miim_end,}
|
|
},
|
|
(struct phy_cmd[]){ /* shutdown - disable interrupts */
|
|
{miim_end,}
|
|
},
|
|
};
|
|
|
|
/* Parse the DP83865's link and auto-neg status register for speed and duplex
|
|
* information
|
|
*/
|
|
uint mii_parse_dp83865_lanr(uint mii_reg, struct tsec_private *priv)
|
|
{
|
|
switch (mii_reg & MIIM_DP83865_SPD_MASK) {
|
|
|
|
case MIIM_DP83865_SPD_1000:
|
|
priv->speed = 1000;
|
|
break;
|
|
|
|
case MIIM_DP83865_SPD_100:
|
|
priv->speed = 100;
|
|
break;
|
|
|
|
default:
|
|
priv->speed = 10;
|
|
break;
|
|
|
|
}
|
|
|
|
if (mii_reg & MIIM_DP83865_DPX_FULL)
|
|
priv->duplexity = 1;
|
|
else
|
|
priv->duplexity = 0;
|
|
|
|
return 0;
|
|
}
|
|
|
|
struct phy_info phy_info_dp83865 = {
|
|
0x20005c7,
|
|
"NatSemi DP83865",
|
|
4,
|
|
(struct phy_cmd[]){ /* config */
|
|
{MIIM_CONTROL, MIIM_DP83865_CR_INIT, NULL},
|
|
{miim_end,}
|
|
},
|
|
(struct phy_cmd[]){ /* startup */
|
|
/* Status is read once to clear old link state */
|
|
{MIIM_STATUS, miim_read, NULL},
|
|
/* Auto-negotiate */
|
|
{MIIM_STATUS, miim_read, &mii_parse_sr},
|
|
/* Read the link and auto-neg status */
|
|
{MIIM_DP83865_LANR, miim_read,
|
|
&mii_parse_dp83865_lanr},
|
|
{miim_end,}
|
|
},
|
|
(struct phy_cmd[]){ /* shutdown */
|
|
{miim_end,}
|
|
},
|
|
};
|
|
|
|
struct phy_info *phy_info[] = {
|
|
&phy_info_cis8204,
|
|
&phy_info_cis8201,
|
|
&phy_info_M88E1011S,
|
|
&phy_info_M88E1111S,
|
|
&phy_info_M88E1145,
|
|
&phy_info_dm9161,
|
|
&phy_info_lxt971,
|
|
&phy_info_VSC8244,
|
|
&phy_info_dp83865,
|
|
NULL
|
|
};
|
|
|
|
/* Grab the identifier of the device's PHY, and search through
|
|
* all of the known PHYs to see if one matches. If so, return
|
|
* it, if not, return NULL
|
|
*/
|
|
struct phy_info *get_phy_info(struct eth_device *dev)
|
|
{
|
|
struct tsec_private *priv = (struct tsec_private *)dev->priv;
|
|
uint phy_reg, phy_ID;
|
|
int i;
|
|
struct phy_info *theInfo = NULL;
|
|
|
|
/* Grab the bits from PHYIR1, and put them in the upper half */
|
|
phy_reg = read_phy_reg(priv, MIIM_PHYIR1);
|
|
phy_ID = (phy_reg & 0xffff) << 16;
|
|
|
|
/* Grab the bits from PHYIR2, and put them in the lower half */
|
|
phy_reg = read_phy_reg(priv, MIIM_PHYIR2);
|
|
phy_ID |= (phy_reg & 0xffff);
|
|
|
|
/* loop through all the known PHY types, and find one that */
|
|
/* matches the ID we read from the PHY. */
|
|
for (i = 0; phy_info[i]; i++) {
|
|
if (phy_info[i]->id == (phy_ID >> phy_info[i]->shift))
|
|
theInfo = phy_info[i];
|
|
}
|
|
|
|
if (theInfo == NULL) {
|
|
printf("%s: PHY id %x is not supported!\n", dev->name, phy_ID);
|
|
return NULL;
|
|
} else {
|
|
debug("%s: PHY is %s (%x)\n", dev->name, theInfo->name, phy_ID);
|
|
}
|
|
|
|
return theInfo;
|
|
}
|
|
|
|
/* Execute the given series of commands on the given device's
|
|
* PHY, running functions as necessary
|
|
*/
|
|
void phy_run_commands(struct tsec_private *priv, struct phy_cmd *cmd)
|
|
{
|
|
int i;
|
|
uint result;
|
|
volatile tsec_t *phyregs = priv->phyregs;
|
|
|
|
phyregs->miimcfg = MIIMCFG_RESET;
|
|
|
|
phyregs->miimcfg = MIIMCFG_INIT_VALUE;
|
|
|
|
while (phyregs->miimind & MIIMIND_BUSY) ;
|
|
|
|
for (i = 0; cmd->mii_reg != miim_end; i++) {
|
|
if (cmd->mii_data == miim_read) {
|
|
result = read_phy_reg(priv, cmd->mii_reg);
|
|
|
|
if (cmd->funct != NULL)
|
|
(*(cmd->funct)) (result, priv);
|
|
|
|
} else {
|
|
if (cmd->funct != NULL)
|
|
result = (*(cmd->funct)) (cmd->mii_reg, priv);
|
|
else
|
|
result = cmd->mii_data;
|
|
|
|
write_phy_reg(priv, cmd->mii_reg, result);
|
|
|
|
}
|
|
cmd++;
|
|
}
|
|
}
|
|
|
|
/* Relocate the function pointers in the phy cmd lists */
|
|
static void relocate_cmds(void)
|
|
{
|
|
struct phy_cmd **cmdlistptr;
|
|
struct phy_cmd *cmd;
|
|
int i, j, k;
|
|
|
|
for (i = 0; phy_info[i]; i++) {
|
|
/* First thing's first: relocate the pointers to the
|
|
* PHY command structures (the structs were done) */
|
|
phy_info[i] = (struct phy_info *)((uint) phy_info[i]
|
|
+ gd->reloc_off);
|
|
phy_info[i]->name += gd->reloc_off;
|
|
phy_info[i]->config =
|
|
(struct phy_cmd *)((uint) phy_info[i]->config
|
|
+ gd->reloc_off);
|
|
phy_info[i]->startup =
|
|
(struct phy_cmd *)((uint) phy_info[i]->startup
|
|
+ gd->reloc_off);
|
|
phy_info[i]->shutdown =
|
|
(struct phy_cmd *)((uint) phy_info[i]->shutdown
|
|
+ gd->reloc_off);
|
|
|
|
cmdlistptr = &phy_info[i]->config;
|
|
j = 0;
|
|
for (; cmdlistptr <= &phy_info[i]->shutdown; cmdlistptr++) {
|
|
k = 0;
|
|
for (cmd = *cmdlistptr;
|
|
cmd->mii_reg != miim_end;
|
|
cmd++) {
|
|
/* Only relocate non-NULL pointers */
|
|
if (cmd->funct)
|
|
cmd->funct += gd->reloc_off;
|
|
|
|
k++;
|
|
}
|
|
j++;
|
|
}
|
|
}
|
|
|
|
relocated = 1;
|
|
}
|
|
|
|
#if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII) \
|
|
&& !defined(BITBANGMII)
|
|
|
|
struct tsec_private *get_priv_for_phy(unsigned char phyaddr)
|
|
{
|
|
int i;
|
|
|
|
for (i = 0; i < MAXCONTROLLERS; i++) {
|
|
if (privlist[i]->phyaddr == phyaddr)
|
|
return privlist[i];
|
|
}
|
|
|
|
return NULL;
|
|
}
|
|
|
|
/*
|
|
* Read a MII PHY register.
|
|
*
|
|
* Returns:
|
|
* 0 on success
|
|
*/
|
|
static int tsec_miiphy_read(char *devname, unsigned char addr,
|
|
unsigned char reg, unsigned short *value)
|
|
{
|
|
unsigned short ret;
|
|
struct tsec_private *priv = get_priv_for_phy(addr);
|
|
|
|
if (NULL == priv) {
|
|
printf("Can't read PHY at address %d\n", addr);
|
|
return -1;
|
|
}
|
|
|
|
ret = (unsigned short)read_phy_reg(priv, reg);
|
|
*value = ret;
|
|
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* Write a MII PHY register.
|
|
*
|
|
* Returns:
|
|
* 0 on success
|
|
*/
|
|
static int tsec_miiphy_write(char *devname, unsigned char addr,
|
|
unsigned char reg, unsigned short value)
|
|
{
|
|
struct tsec_private *priv = get_priv_for_phy(addr);
|
|
|
|
if (NULL == priv) {
|
|
printf("Can't write PHY at address %d\n", addr);
|
|
return -1;
|
|
}
|
|
|
|
write_phy_reg(priv, reg, value);
|
|
|
|
return 0;
|
|
}
|
|
|
|
#endif /* defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII)
|
|
&& !defined(BITBANGMII) */
|
|
|
|
#endif /* CONFIG_TSEC_ENET */
|
|
|