upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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33 lines
1.3 KiB
33 lines
1.3 KiB
Intel x86 PINCTRL/GPIO controller
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Pin-muxing on x86 can be described with a node for the PINCTRL master
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node and a set of child nodes for each pin on the SoC.
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The PINCTRL master node requires the following properties:
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- compatible : "intel,x86-pinctrl"
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Pin nodes must be children of the pinctrl master node and can
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contain the following properties:
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- pad-offset - (required) offset in the IOBASE for the pin to configure
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- gpio-offset - (required only when 'mode-gpio' is set) 2 cells
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- offset in the GPIOBASE for the pin to configure
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- the bit shift in this register (4 = bit 4)
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- mode-gpio - (optional) standalone property to force the pin into GPIO mode
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- mode-func - (optional) function number to assign to the pin. If
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'mode-gpio' is set, this property will be ignored.
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in case of 'mode-gpio' property set:
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- output-value - (optional) this set the default output value of the GPIO
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- direction - (optional) this set the direction of the gpio
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- pull-strength - (optional) this set the pull strength of the pin
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- pull-assign - (optional) this set the pull assignement (up/down) of the pin
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- invert - (optional) this input pin is inverted
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Example:
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pin_usb_host_en0@0 {
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gpio-offset = <0x80 8>;
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pad-offset = <0x260>;
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mode-gpio;
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output-value = <1>;
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direction = <PIN_OUTPUT>;
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};
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