upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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399 lines
11 KiB
399 lines
11 KiB
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2009 Freescale Semiconductor, Inc.
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/gpio.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/iomux-mx51.h>
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#include <linux/errno.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/arch/crm_regs.h>
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#include <asm/arch/clock.h>
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#include <asm/mach-imx/mx5_video.h>
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#include <i2c.h>
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#include <input.h>
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#include <mmc.h>
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#include <fsl_esdhc.h>
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#include <power/pmic.h>
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#include <fsl_pmic.h>
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#include <mc13892.h>
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#include <usb/ehci-ci.h>
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DECLARE_GLOBAL_DATA_PTR;
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#ifdef CONFIG_FSL_ESDHC
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struct fsl_esdhc_cfg esdhc_cfg[2] = {
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{MMC_SDHC1_BASE_ADDR},
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{MMC_SDHC2_BASE_ADDR},
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};
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#endif
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int dram_init(void)
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{
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/* dram_init must store complete ramsize in gd->ram_size */
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gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
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PHYS_SDRAM_1_SIZE);
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return 0;
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}
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u32 get_board_rev(void)
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{
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u32 rev = get_cpu_rev();
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if (!gpio_get_value(IMX_GPIO_NR(1, 22)))
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rev |= BOARD_REV_2_0 << BOARD_VER_OFFSET;
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return rev;
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}
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#define UART_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN | PAD_CTL_DSE_HIGH)
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static void setup_iomux_uart(void)
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{
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static const iomux_v3_cfg_t uart_pads[] = {
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MX51_PAD_UART1_RXD__UART1_RXD,
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MX51_PAD_UART1_TXD__UART1_TXD,
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NEW_PAD_CTRL(MX51_PAD_UART1_RTS__UART1_RTS, UART_PAD_CTRL),
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NEW_PAD_CTRL(MX51_PAD_UART1_CTS__UART1_CTS, UART_PAD_CTRL),
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};
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imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
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}
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static void setup_iomux_fec(void)
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{
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static const iomux_v3_cfg_t fec_pads[] = {
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NEW_PAD_CTRL(MX51_PAD_EIM_EB2__FEC_MDIO, PAD_CTL_HYS |
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PAD_CTL_PUS_22K_UP | PAD_CTL_ODE |
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PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST),
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MX51_PAD_NANDF_CS3__FEC_MDC,
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NEW_PAD_CTRL(MX51_PAD_EIM_CS3__FEC_RDATA3, MX51_PAD_CTRL_2),
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NEW_PAD_CTRL(MX51_PAD_EIM_CS2__FEC_RDATA2, MX51_PAD_CTRL_2),
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NEW_PAD_CTRL(MX51_PAD_EIM_EB3__FEC_RDATA1, MX51_PAD_CTRL_2),
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MX51_PAD_NANDF_D9__FEC_RDATA0,
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MX51_PAD_NANDF_CS6__FEC_TDATA3,
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MX51_PAD_NANDF_CS5__FEC_TDATA2,
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MX51_PAD_NANDF_CS4__FEC_TDATA1,
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MX51_PAD_NANDF_D8__FEC_TDATA0,
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MX51_PAD_NANDF_CS7__FEC_TX_EN,
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MX51_PAD_NANDF_CS2__FEC_TX_ER,
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MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK,
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NEW_PAD_CTRL(MX51_PAD_NANDF_RB2__FEC_COL, MX51_PAD_CTRL_4),
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NEW_PAD_CTRL(MX51_PAD_NANDF_RB3__FEC_RX_CLK, MX51_PAD_CTRL_4),
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MX51_PAD_EIM_CS5__FEC_CRS,
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MX51_PAD_EIM_CS4__FEC_RX_ER,
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NEW_PAD_CTRL(MX51_PAD_NANDF_D11__FEC_RX_DV, MX51_PAD_CTRL_4),
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};
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imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
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}
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#ifdef CONFIG_MXC_SPI
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static void setup_iomux_spi(void)
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{
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static const iomux_v3_cfg_t spi_pads[] = {
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NEW_PAD_CTRL(MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI, PAD_CTL_HYS |
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PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST),
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NEW_PAD_CTRL(MX51_PAD_CSPI1_MISO__ECSPI1_MISO, PAD_CTL_HYS |
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PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST),
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NEW_PAD_CTRL(MX51_PAD_CSPI1_SS1__ECSPI1_SS1,
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MX51_GPIO_PAD_CTRL),
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MX51_PAD_CSPI1_SS0__ECSPI1_SS0,
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NEW_PAD_CTRL(MX51_PAD_CSPI1_RDY__ECSPI1_RDY, MX51_PAD_CTRL_2),
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NEW_PAD_CTRL(MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK, PAD_CTL_HYS |
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PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST),
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};
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imx_iomux_v3_setup_multiple_pads(spi_pads, ARRAY_SIZE(spi_pads));
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}
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#endif
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#ifdef CONFIG_USB_EHCI_MX5
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#define MX51EVK_USBH1_HUB_RST IMX_GPIO_NR(1, 7)
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#define MX51EVK_USBH1_STP IMX_GPIO_NR(1, 27)
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#define MX51EVK_USB_CLK_EN_B IMX_GPIO_NR(2, 1)
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#define MX51EVK_USB_PHY_RESET IMX_GPIO_NR(2, 5)
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static void setup_usb_h1(void)
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{
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static const iomux_v3_cfg_t usb_h1_pads[] = {
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MX51_PAD_USBH1_CLK__USBH1_CLK,
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MX51_PAD_USBH1_DIR__USBH1_DIR,
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MX51_PAD_USBH1_STP__USBH1_STP,
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MX51_PAD_USBH1_NXT__USBH1_NXT,
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MX51_PAD_USBH1_DATA0__USBH1_DATA0,
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MX51_PAD_USBH1_DATA1__USBH1_DATA1,
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MX51_PAD_USBH1_DATA2__USBH1_DATA2,
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MX51_PAD_USBH1_DATA3__USBH1_DATA3,
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MX51_PAD_USBH1_DATA4__USBH1_DATA4,
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MX51_PAD_USBH1_DATA5__USBH1_DATA5,
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MX51_PAD_USBH1_DATA6__USBH1_DATA6,
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MX51_PAD_USBH1_DATA7__USBH1_DATA7,
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NEW_PAD_CTRL(MX51_PAD_GPIO1_7__GPIO1_7, 0), /* H1 hub reset */
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MX51_PAD_EIM_D17__GPIO2_1,
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MX51_PAD_EIM_D21__GPIO2_5, /* PHY reset */
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};
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imx_iomux_v3_setup_multiple_pads(usb_h1_pads, ARRAY_SIZE(usb_h1_pads));
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}
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int board_ehci_hcd_init(int port)
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{
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/* Set USBH1_STP to GPIO and toggle it */
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imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX51_PAD_USBH1_STP__GPIO1_27,
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MX51_USBH_PAD_CTRL));
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gpio_direction_output(MX51EVK_USBH1_STP, 0);
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gpio_direction_output(MX51EVK_USB_PHY_RESET, 0);
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mdelay(10);
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gpio_set_value(MX51EVK_USBH1_STP, 1);
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/* Set back USBH1_STP to be function */
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imx_iomux_v3_setup_pad(MX51_PAD_USBH1_STP__USBH1_STP);
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/* De-assert USB PHY RESETB */
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gpio_set_value(MX51EVK_USB_PHY_RESET, 1);
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/* Drive USB_CLK_EN_B line low */
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gpio_direction_output(MX51EVK_USB_CLK_EN_B, 0);
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/* Reset USB hub */
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gpio_direction_output(MX51EVK_USBH1_HUB_RST, 0);
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mdelay(2);
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gpio_set_value(MX51EVK_USBH1_HUB_RST, 1);
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return 0;
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}
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#endif
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static void power_init(void)
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{
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unsigned int val;
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struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)MXC_CCM_BASE;
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struct pmic *p;
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int ret;
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ret = pmic_init(CONFIG_FSL_PMIC_BUS);
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if (ret)
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return;
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p = pmic_get("FSL_PMIC");
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if (!p)
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return;
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/* Write needed to Power Gate 2 register */
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pmic_reg_read(p, REG_POWER_MISC, &val);
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val &= ~PWGT2SPIEN;
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pmic_reg_write(p, REG_POWER_MISC, val);
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/* Externally powered */
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pmic_reg_read(p, REG_CHARGE, &val);
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val |= ICHRG0 | ICHRG1 | ICHRG2 | ICHRG3 | CHGAUTOB;
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pmic_reg_write(p, REG_CHARGE, val);
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/* power up the system first */
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pmic_reg_write(p, REG_POWER_MISC, PWUP);
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/* Set core voltage to 1.1V */
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pmic_reg_read(p, REG_SW_0, &val);
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val = (val & ~SWx_VOLT_MASK) | SWx_1_100V;
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pmic_reg_write(p, REG_SW_0, val);
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/* Setup VCC (SW2) to 1.25 */
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pmic_reg_read(p, REG_SW_1, &val);
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val = (val & ~SWx_VOLT_MASK) | SWx_1_250V;
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pmic_reg_write(p, REG_SW_1, val);
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/* Setup 1V2_DIG1 (SW3) to 1.25 */
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pmic_reg_read(p, REG_SW_2, &val);
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val = (val & ~SWx_VOLT_MASK) | SWx_1_250V;
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pmic_reg_write(p, REG_SW_2, val);
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udelay(50);
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/* Raise the core frequency to 800MHz */
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writel(0x0, &mxc_ccm->cacrr);
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/* Set switchers in Auto in NORMAL mode & STANDBY mode */
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/* Setup the switcher mode for SW1 & SW2*/
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pmic_reg_read(p, REG_SW_4, &val);
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val = (val & ~((SWMODE_MASK << SWMODE1_SHIFT) |
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(SWMODE_MASK << SWMODE2_SHIFT)));
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val |= (SWMODE_AUTO_AUTO << SWMODE1_SHIFT) |
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(SWMODE_AUTO_AUTO << SWMODE2_SHIFT);
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pmic_reg_write(p, REG_SW_4, val);
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/* Setup the switcher mode for SW3 & SW4 */
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pmic_reg_read(p, REG_SW_5, &val);
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val = (val & ~((SWMODE_MASK << SWMODE3_SHIFT) |
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(SWMODE_MASK << SWMODE4_SHIFT)));
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val |= (SWMODE_AUTO_AUTO << SWMODE3_SHIFT) |
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(SWMODE_AUTO_AUTO << SWMODE4_SHIFT);
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pmic_reg_write(p, REG_SW_5, val);
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/* Set VDIG to 1.65V, VGEN3 to 1.8V, VCAM to 2.6V */
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pmic_reg_read(p, REG_SETTING_0, &val);
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val &= ~(VCAM_MASK | VGEN3_MASK | VDIG_MASK);
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val |= VDIG_1_65 | VGEN3_1_8 | VCAM_2_6;
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pmic_reg_write(p, REG_SETTING_0, val);
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/* Set VVIDEO to 2.775V, VAUDIO to 3V, VSD to 3.15V */
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pmic_reg_read(p, REG_SETTING_1, &val);
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val &= ~(VVIDEO_MASK | VSD_MASK | VAUDIO_MASK);
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val |= VSD_3_15 | VAUDIO_3_0 | VVIDEO_2_775;
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pmic_reg_write(p, REG_SETTING_1, val);
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/* Configure VGEN3 and VCAM regulators to use external PNP */
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val = VGEN3CONFIG | VCAMCONFIG;
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pmic_reg_write(p, REG_MODE_1, val);
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udelay(200);
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/* Enable VGEN3, VCAM, VAUDIO, VVIDEO, VSD regulators */
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val = VGEN3EN | VGEN3CONFIG | VCAMEN | VCAMCONFIG |
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VVIDEOEN | VAUDIOEN | VSDEN;
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pmic_reg_write(p, REG_MODE_1, val);
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imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX51_PAD_EIM_A20__GPIO2_14,
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NO_PAD_CTRL));
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gpio_direction_output(IMX_GPIO_NR(2, 14), 0);
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udelay(500);
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gpio_set_value(IMX_GPIO_NR(2, 14), 1);
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}
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#ifdef CONFIG_FSL_ESDHC
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int board_mmc_getcd(struct mmc *mmc)
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{
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struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
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int ret;
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imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX51_PAD_GPIO1_0__GPIO1_0,
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NO_PAD_CTRL));
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gpio_direction_input(IMX_GPIO_NR(1, 0));
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imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX51_PAD_GPIO1_6__GPIO1_6,
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NO_PAD_CTRL));
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gpio_direction_input(IMX_GPIO_NR(1, 6));
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if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR)
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ret = !gpio_get_value(IMX_GPIO_NR(1, 0));
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else
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ret = !gpio_get_value(IMX_GPIO_NR(1, 6));
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return ret;
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}
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int board_mmc_init(bd_t *bis)
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{
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static const iomux_v3_cfg_t sd1_pads[] = {
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NEW_PAD_CTRL(MX51_PAD_SD1_CMD__SD1_CMD, PAD_CTL_DSE_MAX |
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PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST),
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NEW_PAD_CTRL(MX51_PAD_SD1_CLK__SD1_CLK, PAD_CTL_DSE_MAX |
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PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST),
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NEW_PAD_CTRL(MX51_PAD_SD1_DATA0__SD1_DATA0, PAD_CTL_DSE_MAX |
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PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST),
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NEW_PAD_CTRL(MX51_PAD_SD1_DATA1__SD1_DATA1, PAD_CTL_DSE_MAX |
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PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST),
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NEW_PAD_CTRL(MX51_PAD_SD1_DATA2__SD1_DATA2, PAD_CTL_DSE_MAX |
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PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST),
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NEW_PAD_CTRL(MX51_PAD_SD1_DATA3__SD1_DATA3, PAD_CTL_DSE_MAX |
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PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN | PAD_CTL_SRE_FAST),
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NEW_PAD_CTRL(MX51_PAD_GPIO1_0__SD1_CD, PAD_CTL_HYS),
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NEW_PAD_CTRL(MX51_PAD_GPIO1_1__SD1_WP, PAD_CTL_HYS),
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};
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static const iomux_v3_cfg_t sd2_pads[] = {
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NEW_PAD_CTRL(MX51_PAD_SD2_CMD__SD2_CMD,
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PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST),
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NEW_PAD_CTRL(MX51_PAD_SD2_CLK__SD2_CLK,
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PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST),
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NEW_PAD_CTRL(MX51_PAD_SD2_DATA0__SD2_DATA0,
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PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST),
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NEW_PAD_CTRL(MX51_PAD_SD2_DATA1__SD2_DATA1,
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PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST),
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NEW_PAD_CTRL(MX51_PAD_SD2_DATA2__SD2_DATA2,
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PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST),
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NEW_PAD_CTRL(MX51_PAD_SD2_DATA3__SD2_DATA3,
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PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST),
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NEW_PAD_CTRL(MX51_PAD_GPIO1_6__GPIO1_6, PAD_CTL_HYS),
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NEW_PAD_CTRL(MX51_PAD_GPIO1_5__GPIO1_5, PAD_CTL_HYS),
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};
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u32 index;
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int ret;
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esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
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esdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
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for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM;
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index++) {
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switch (index) {
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case 0:
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imx_iomux_v3_setup_multiple_pads(sd1_pads,
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ARRAY_SIZE(sd1_pads));
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break;
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case 1:
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imx_iomux_v3_setup_multiple_pads(sd2_pads,
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ARRAY_SIZE(sd2_pads));
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break;
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default:
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printf("Warning: you configured more ESDHC controller"
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"(%d) as supported by the board(2)\n",
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CONFIG_SYS_FSL_ESDHC_NUM);
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return -EINVAL;
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}
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ret = fsl_esdhc_initialize(bis, &esdhc_cfg[index]);
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if (ret)
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return ret;
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}
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return 0;
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}
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#endif
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int board_early_init_f(void)
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{
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setup_iomux_uart();
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setup_iomux_fec();
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#ifdef CONFIG_USB_EHCI_MX5
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setup_usb_h1();
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#endif
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setup_iomux_lcd();
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return 0;
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}
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int board_init(void)
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{
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/* address of boot parameters */
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gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
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return 0;
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}
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#ifdef CONFIG_BOARD_LATE_INIT
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int board_late_init(void)
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{
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#ifdef CONFIG_MXC_SPI
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setup_iomux_spi();
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power_init();
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#endif
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return 0;
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}
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#endif
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/*
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* Do not overwrite the console
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* Use always serial for U-Boot console
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*/
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int overwrite_console(void)
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{
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return 1;
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}
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int checkboard(void)
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{
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puts("Board: MX51EVK\n");
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return 0;
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}
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